Product
Folder Sample &
Buy Technical
Documents Support &
Community Tools &
Software SN65DSI86-Q1
SLLSEJ5A – JULY 2014 – REVISED DECEMBER 2015 SN65DSIx6-Q1 MIPI® DSI to eDP™ Bridge
1 Features 3 Description The SN65DSI86-Q1 DSI to embedded DisplayPort
(eDP) bridge features a dual-channel MIPI D-PHY
receiver front-end configuration with four lanes per
channel operating at 1.5 Gbps per lane and a
maximum input bandwidth of 12 Gbps. The bridge
decodes MIPI DSI 18-bpp RGB666 and 24-bpp
RGB888 packets and converts the formatted video
data stream to a DisplayPort with up to four lanes at
either 1.62 Gbps, 2.16 Gbps, 2.43 Gbps, 2.7 Gbps,
3.24 Gbps, 4.32 Gbps, or 5.4 Gbps. 1 Embedded DisplayPortв„ў (eDPв„ў) 1.4 Compliant
Supporting 1, 2, or 4 Lanes at 1.62 Gbps (RBR),
2.16 Gbps, 2.43 Gbps, 2.7 Gbps (HBR), 3.24
Gbps, 4.32 Gbps, or 5.4 Gbps (HBR2).
Implements MIPIВ® D-PHY Version 1.1 Physical
Layer Front-End and Display Serial Interface (DSI)
Version 1.02.00 …
