Datasheet Texas Instruments SN54HC74J — 数据表

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SCLS094E – DECEMBER 1982 – REVISED DECEMBER 2015 SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset
1 Features 3 Description The SNx4HC74 devices contain two independent Dtype positive-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or resets
the outputs, regardless of the levels of the other
inputs. When PRE and CLR are inactive (high), data
at the data (D) input meeting the setup time
requirements are transferred to the outputs on the
positive-going edge of the clock (CLK) pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of CLK. Following the holdtime interval, data at the D input can be changed
without affecting the levels at the outputs. 1 Wide Operating Voltage Range: 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 40-ВµA Maximum ICC
Typical tpd = 15 ns
В±4-mA Output Drive at 5 V
Very Low Input Current of 1 ВµA 2 Applications Ultrasound System
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