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Documents SN54HC164, SN74HC164
SCLS115G – DECEMBER 1982 – REVISED SEPTEMBER 2015 SNx4HC164 8-Bit Parallel-Out Serial Shift Registers
1 Features 3 Description These 8-bit shift registers feature AND-gated serial
inputs and an asynchronous clear (CLR) input. The
gated serial (A and B) inputs permit complete control
over incoming data; a low at either input inhibits entry
of the new data and resets the first flip-flop to the low
level at the next clock (CLK) pulse. A high-level input
enables the other input, which then determines the
state of the first flip-flop. Data at the serial inputs can
be changed while CLK is high or low, provided the
minimum set-up time requirements are met. Clocking
occurs on the low-to-high-level transition of CLK. 1 Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up to 10 LSTTL Loads
Low Power Consumption, 80-ОјA Maximum ICC
Typical tpd = 20 ns
В±4-mA Output Drive at 5 V
Low Input Current of 1-ОјA Maximum …
