Datasheet Texas Instruments SN54ACT04 — 数据表

制造商Texas Instruments
系列SN54ACT04
Datasheet Texas Instruments SN54ACT04

六角逆变器

数据表

SN54ACT04, SN74ACT04 datasheet
PDF, 1.2 Mb, 修订版: C, 档案已发布: Oct 23, 2003
从文件中提取

价格

状态

5962-89734012A5962-8973401CA5962-8973401DASNJ54ACT04FKSNJ54ACT04JSNJ54ACT04W
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNo

打包

5962-89734012A5962-8973401CA5962-8973401DASNJ54ACT04FKSNJ54ACT04JSNJ54ACT04W
N123456
Pin201414201414
Package TypeFKJWFKJW
Industry STD TermLCCCCDIPCFPLCCCCDIPCFP
JEDEC CodeS-CQCC-NR-GDIP-TR-GDFP-FS-CQCC-NR-GDIP-TR-GDFP-F
Package QTY111111
CarrierTUBETUBETUBETUBETUBETUBE
Width (mm)8.896.675.978.896.675.97
Length (mm)8.8919.569.218.8919.569.21
Thickness (mm)1.834.571.591.834.571.59
Pitch (mm)1.272.541.271.272.541.27
Max Height (mm)2.035.082.032.035.082.03
Mechanical Data下载下载下载下载下载下载
Device MarkingSNJ54ACT5962-8973401CA5962-8973401DA

参数化

Parameters / Models5962-89734012A
5962-89734012A
5962-8973401CA
5962-8973401CA
5962-8973401DA
5962-8973401DA
SNJ54ACT04FK
SNJ54ACT04FK
SNJ54ACT04J
SNJ54ACT04J
SNJ54ACT04W
SNJ54ACT04W
Bits666666
Input TypeTTLTTLTTLTTLTTLTTL
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output TypeCMOSCMOSCMOSCMOSCMOSCMOS
Package GroupLCCCCDIPCFPLCCCCDIPCFP
Package Size: mm2:W x L, PKG20LCCC: 79 mm2: 8.89 x 8.89(LCCC)See datasheet (CDIP)See datasheet (CFP)20LCCC: 79 mm2: 8.89 x 8.89(LCCC)See datasheet (CDIP)See datasheet (CFP)
RatingMilitaryMilitaryMilitaryMilitaryMilitaryMilitary
Schmitt TriggerNoNoNoNoNoNo
Technology FamilyACTACTACTACTACTACT
VCC(Max), V5.55.55.55.55.55.5
VCC(Min), V4.54.54.54.54.54.5
Voltage(Nom), V555555

生态计划

5962-89734012A5962-8973401CA5962-8973401DASNJ54ACT04FKSNJ54ACT04JSNJ54ACT04W
RoHSSee ti.comSee ti.comSee ti.comSee ti.comSee ti.comSee ti.com

应用须知

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    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
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  • CMOS Power Consumption and CPD Calculation (Rev. B)
    PDF, 89 Kb, 修订版: B, 档案已发布: Jun 1, 1997
    Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
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    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

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制造商分类

  • Semiconductors> Space & High Reliability> Logic Products> Buffers/Drivers/Transceivers> Buffer Drivers