Datasheet Texas Instruments LP2996A — 数据表
| 制造商 | Texas Instruments |
| 系列 | LP2996A |
具有关断引脚的1.5A DDR终端调节器
数据表
状态
| LP2996AMR/NOPB | LP2996AMRE/NOPB | LP2996AMRX/NOPB | |
|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No | No |
打包
| LP2996AMR/NOPB | LP2996AMRE/NOPB | LP2996AMRX/NOPB | |
|---|---|---|---|
| N | 1 | 2 | 3 |
| Pin | 8 | 8 | 8 |
| Package Type | DDA | DDA | DDA |
| Industry STD Term | HSOIC | HSOIC | HSOIC |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 95 | 250 | 2500 |
| Carrier | TUBE | SMALL T&R | LARGE T&R |
| Device Marking | LP2996 | AMR | AMR |
| Width (mm) | 3.9 | 3.9 | 3.9 |
| Length (mm) | 4.89 | 4.89 | 4.89 |
| Thickness (mm) | 1.48 | 1.48 | 1.48 |
| Pitch (mm) | 1.27 | 1.27 | 1.27 |
| Max Height (mm) | 1.7 | 1.7 | 1.7 |
| Mechanical Data | 下载 | 下载 | 下载 |
参数化
| Parameters / Models | LP2996AMR/NOPB | LP2996AMRE/NOPB | LP2996AMRX/NOPB |
|---|---|---|---|
| Control Mode | N/A | N/A | N/A |
| DDR Memory Type | DDR,DDR2,DDR3,DDR3L | DDR,DDR2,DDR3,DDR3L | DDR,DDR2,DDR3,DDR3L |
| Iout VTT(Max), A | 1.5 | 1.5 | 1.5 |
| Iq(Typ), mA | 0.32 | 0.32 | 0.32 |
| Operating Temperature Range, C | 0 to 125 | 0 to 125 | 0 to 125 |
| Output | VREF,VTT | VREF,VTT | VREF,VTT |
| Package Group | SO PowerPAD | SO PowerPAD | SO PowerPAD |
| Package Size: mm2:W x L, PKG | 8SO PowerPAD: 29 mm2: 6 x 4.9(SO PowerPAD) | 8SO PowerPAD: 29 mm2: 6 x 4.9(SO PowerPAD) | 8SO PowerPAD: 29 mm2: 6 x 4.9(SO PowerPAD) |
| Rating | Catalog | Catalog | Catalog |
| Regulator Type | Linear Regulator | Linear Regulator | Linear Regulator |
| Special Features | Shutdown Pin for S3 | Shutdown Pin for S3 | Shutdown Pin for S3 |
| Vin Bias(Max), V | 5.5 | 5.5 | 5.5 |
| Vin Bias(Min), V | 2.2 | 2.2 | 2.2 |
| Vin(Max), V | 5.5 | 5.5 | 5.5 |
| Vin(Min), V | 1.35 | 1.35 | 1.35 |
| Vout VTT(Min), V | 0.677 | 0.677 | 0.677 |
生态计划
| LP2996AMR/NOPB | LP2996AMRE/NOPB | LP2996AMRX/NOPB | |
|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant |
应用须知
- Limiting DDR Termination Regulators’ Inrush CurrentPDF, 772 Kb, 档案已发布: Aug 23, 2016
The output voltage of DDR termination regulators tends to rise quickly after their VDDQ line is enabled. Most DDR terminators are specifically designed for fast start-up. They also require bulky output capacitors for a stable output voltage. This often results in a significant inrush current from DDR terminator voltage supply to charge the output capacitors and to provide curre
模型线
系列: LP2996A (3)
制造商分类
- Semiconductors> Power Management> DDR Memory Power Solutions