Datasheet Texas Instruments LMK04616 — 数据表
| 制造商 | Texas Instruments |
| 系列 | LMK04616 |
符合JESD204B标准的超低噪声和低功耗时钟抖动消除器
数据表
LMK04616 Ultra-Low Noise and Low Power JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs datasheet
PDF, 1.8 Mb, 修订版: A, 档案已发布: Jun 22, 2017
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状态
| LMK04616ZCRR | LMK04616ZCRT | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No |
打包
| LMK04616ZCRR | LMK04616ZCRT | |
|---|---|---|
| N | 1 | 2 |
| Pin | 144 | 144 |
| Package Type | ZCR | ZCR |
| Industry STD Term | NFBGA | NFBGA |
| JEDEC Code | S-PBGA-N | S-PBGA-N |
| Package QTY | 1000 | 250 |
| Carrier | LARGE T&R | SMALL T&R |
| Device Marking | LMK04616 | LMK04616 |
| Width (mm) | 10 | 10 |
| Length (mm) | 10 | 10 |
| Thickness (mm) | .95 | .95 |
| Pitch (mm) | .8 | .8 |
| Max Height (mm) | 1.5 | 1.5 |
| Mechanical Data | 下载 | 下载 |
参数化
| Parameters / Models | LMK04616ZCRR | LMK04616ZCRT |
|---|---|---|
| Number of Inputs | 4 | 4 |
| Number of Outputs | 16 | 16 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Output Frequency(Max), MHz | 2000 | 2000 |
| Output Frequency(Min), MHz | 0.03 | 0.03 |
| Output Level | HCSL,HSDS,LVDS,LVPECL | HCSL,HSDS,LVDS,LVPECL |
| Package Group | NFBGA | NFBGA |
| Package Size: mm2:W x L, PKG | 144NFBGA: 100 mm2: 10 x 10(NFBGA) | 144NFBGA: 100 mm2: 10 x 10(NFBGA) |
| RMS Jitter | 0.065 | 0.065 |
| Rating | Catalog | Catalog |
| Special Features | 105C PCB temp,Holdover mode,JESD204B SYSREF Generation,Manual and automatic switching between inputs,SPI | 105C PCB temp,Holdover mode,JESD204B SYSREF Generation,Manual and automatic switching between inputs,SPI |
| Supply Voltage(Max), V | 3.465 | 3.465 |
| Supply Voltage(Min), V | 1.7 | 1.7 |
| VCO Frequency(Max), MHz | 6200 | 6200 |
| VCO Frequency(Min), MHz | 5800 | 5800 |
生态计划
| LMK04616ZCRR | LMK04616ZCRT | |
|---|---|---|
| RoHS | Compliant | Compliant |
模型线
系列: LMK04616 (2)
制造商分类
- Semiconductors> Clock and Timing> Clock Jitter Cleaners> Dual / Cascaded PLL