Datasheet Texas Instruments DS92LV1212 — 数据表

DS92LV1212 DS92LV1212 16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer with
Embedded Clock Recovery Literature Number: SNLS050 DS92LV1212
16-40 MHz 10-Bit Bus LVDS Random Lock Deserializer
with Embedded Clock Recovery
General Description Features The DS92LV1212 is an upgrade of the DS92LV1210. It
maintains all of the features of the DS92LV1210 with the additional capability of locking to the incoming data stream
without the need of SYNC patterns. This makes the
DS92LV1212 useful in applications where the Deserializer
must be operated “open-loop” — without a feedback path
from the Deserializer to the Serializer. The DS92LV1212 is
designed to be used with the DS92LV1021 Bus LVDS Serializer. The DS92LV1212 receives a Bus LVDS serial data
stream and transforms it into a 10-bit wide parallel data bus
and separate clock. The reduced cable, PCB trace count
and connector size saves cost and makes PCB layout
easier. Clock-to-data and data-to-data skews are eliminated
since one input receives both clock and data bits serially.
The powerdown pin is used to save power by reducing the
supply current when the device is not in use. The Deserializer will establish lock to a synchronization pattern within
specified lock times but it can also lock to a data stream without SYNC patterns. n Clock recovery without SYNC patterns-random lock
n Guaranteed transition every data transfer cycle
n Chipset (Tx + Rx) power consumption < 300mW (typ) @
40MHz
n Single differential pair eliminates multi-channel skew …