Datasheet Texas Instruments DS90CR481 — 数据表

DS90CR481, DS90CR482
www.ti.com SNLS137D – NOVEMBER 2000 – REVISED APRIL 2013 DS90CR481 / DS90CR482 48-Bit LVDS Channel Link SER/DES -65 -112 MHz
Check for Samples: DS90CR481, DS90CR482 FEATURES 1 2 3.168 Gbits/sec Bandwidth with 66 MHz Clock
5.376 Gbits/sec Bandwidth with 112 MHz Clock
65 -112 MHz Input Clock Support
LVDS SER/DES Reduces Cable and Connector
Size
Pre-Emphasis Reduces Cable Loading Effects
Optional DC Balance Encoding Reduces ISI
Distortion
Cable Deskew of +/-1 LVDS Data Bit Time (up
to 80 MHz Clock Rate)
5V Tolerant TxIN and Control Input Pins
Flow Through Pinout for Easy PCB Design
+3.3V Supply Voltage
Transmitter Rejects Cycle-to-Cycle Jitter
Conforms to ANSI/TIA/EIA-644-1995 LVDS
Standard DESCRIPTION
The DS90CR481 transmitter converts 48 bits of
CMOS/TTL data into eight LVDS (Low Voltage
Differential Signaling) data streams. A phase-locked
transmit clock is transmitted in parallel with the data
streams over a ninth LVDS link. Every cycle of the …