Datasheet Texas Instruments DS25BR110 — 数据表
| 制造商 | Texas Instruments |
| 系列 | DS25BR110 |
具有接收均衡功能的3.125 Gbps LVDS缓冲器
数据表
DS25BR110 3.125 Gbps LVDS Buffer with Receive Equalization datasheet
PDF, 879 Kb, 修订版: E, 档案已发布: Apr 14, 2013
从文件中提取
价格
状态
| DS25BR110TSD/NOPB | DS25BR110TSDX/NOPB | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | Yes |
打包
| DS25BR110TSD/NOPB | DS25BR110TSDX/NOPB | |
|---|---|---|
| N | 1 | 2 |
| Pin | 8 | 8 |
| Package Type | NGQ | NGQ |
| Industry STD Term | WSON | WSON |
| JEDEC Code | S-PDSO-N | S-PDSO-N |
| Package QTY | 1000 | 4500 |
| Carrier | SMALL T&R | LARGE T&R |
| Device Marking | 2R110 | 2R110 |
| Width (mm) | 3 | 3 |
| Length (mm) | 3 | 3 |
| Thickness (mm) | .8 | .8 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | .8 | .8 |
| Mechanical Data | 下载 | 下载 |
参数化
| Parameters / Models | DS25BR110TSD/NOPB | DS25BR110TSDX/NOPB |
|---|---|---|
| Device Type | Buffer | Buffer |
| ESD HBM, kV | 7 | 7 |
| Function | Equalizer | Equalizer |
| ICC(Max), mA | 43 | 43 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Package Group | WSON | WSON |
| Package Size: mm2:W x L, PKG | See datasheet (WSON) | See datasheet (WSON) |
| Protocols | LVDS | LVDS |
生态计划
| DS25BR110TSD/NOPB | DS25BR110TSDX/NOPB | |
|---|---|---|
| RoHS | Compliant | Compliant |
应用须知
- Extending the Signal Path Over Data Trans Lines Using LVDS Signal ConditioningPDF, 575 Kb, 档案已发布: Aug 2, 2007
- LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A)PDF, 101 Kb, 修订版: A, 档案已发布: Apr 29, 2013
This application note introduces Texas Instrument’s LVDS devices with built-in pre-emphasis andequalization circuits, recommends when it makes sense to employ them with the FPD-Link II SER/DES,shows how to optimally interface them to the SER/DES, and discusses distance gains that may berealized with their signal enhancing functions. - AN-1957 LVDS Signal Conditioners Reduce Data-Dependent Jitter (Rev. A)PDF, 275 Kb, 修订版: A, 档案已发布: Apr 26, 2013
Jitter is a phenomenon troubling many designers of high-speed interfaces. It reduces available timingmargin, limits transmission distance between a transmitter and a receiver, and increases system cost bydemanding better performing and more expensive interconnects. LVDS interfaces are not spared fromthese ill effects as they now operate at bit rates exceeding the 3 Gbps mark. Texas Instrumen
模型线
系列: DS25BR110 (2)
制造商分类
- Semiconductors> Interface> Signal Conditioners> Equalizer