Datasheet Texas Instruments DAC38RF96IAAVR — 数据表

制造商Texas Instruments
系列DAC38RF96
零件号DAC38RF96IAAVR
Datasheet Texas Instruments DAC38RF96IAAVR

双通道,14位,9-GSPS,12x-24x内插,9 GHz GSM PLL数模转换器(DAC)144-FCBGA -40至85

数据表

DAC38RFxx Dual-Channel, Single-Ended, 14-Bit, 6- and 9-GSPS, RF-Sampling DAC With JESD204B Interface and On-Chip GSM PLL datasheet
PDF, 3.5 Mb, 修订版: B, 档案已发布: Jul 31, 2017
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin144
Package TypeAAV
Industry STD TermFCBGA
JEDEC CodeS-PBGA-N
Package QTY1000
CarrierLARGE T&R
Device MarkingDAC38RF96I
Width (mm)10
Length (mm)10
Thickness (mm)1.45
Pitch (mm).8
Max Height (mm)1.94
Mechanical Data下载

参数化

ArchitectureCurrent Source
DAC Channels2
InterfaceJESD204B
Interpolation12x,16x,18x,20x,24x
Operating Temperature Range-40 to 85 C
Package GroupFCBGA
Package Size: mm2:W x LSee datasheet (FCBGA) PKG
Power Consumption(Typ)3800 mW
RatingCatalog
Resolution14 Bits
SFDR72 dB
Sample / Update Rate9000 MSPS

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: DAC38RF86EVM
    DAC38RF86 Dual-Channel, 14-Bit, 9-GSPS, 6x-24x Interpolating, 9 GHz GSM PLL DAC Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • DAC38RF8x Test Modes
    PDF, 3.0 Mb, 档案已发布: Jul 25, 2017
    The DAC38RF8x family of devices comes equipped with multiple test modes to assist users in verifying systems in rapid prototyping situations. This application report covers two of the available tests, the pseudorandom binary-sequence test and JESD204B short pattern test, in detail using the TI DAC38RF8xEVM and TSW14J56EVM capture card.
  • Quick-Start Methods in Simulating the DAC38RF8x Input/Output Buffer Information
    PDF, 600 Kb, 档案已发布: Aug 2, 2017
    Input/output Buffer Information Specification (IBIS) models are used to simulate digital electrical interfaces.These models can be categorized into two main categories: traditional and algorithmic modeling interface(AMI). AMI is typically used for SerDes channel simulation, and is different from the traditional IBIS model,which is the focus of this document. These models are simple ASCII tex
  • Eye Scan Testing with the DAC38RFxx
    PDF, 3.6 Mb, 档案已发布: Aug 10, 2017
    The DAC38RFxx family of devices comes equipped with the capability to generate eye diagrams by usinging JTAG communication with the DAC38RF8x eye scan GUI software. By running this software, users can generate eye diagrams to compare with the JESD204B standard eye mask requirements, and verify signal integrity performance of the SerDes link between DAC and FPGA/ASIC. This application report descri

模型线

系列: DAC38RF96 (2)

制造商分类

  • Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)