Datasheet Texas Instruments CDCVF111FNG4 — 数据表

制造商	Texas Instruments
系列	CDCVF111
零件号	CDCVF111FNG4

1：9差分LVPECL时钟驱动器28-PLCC -40至85

数据表

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PDF, 951 Kb, 修订版: B, 档案已发布: Jun 7, 2002

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状态

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	Yes

打包

Pin	28
Package Type	FN
Industry STD Term	PLCC
JEDEC Code	S-PQCC-J
Package QTY	37
Carrier	TUBE
Device Marking	CDCVF111
Width (mm)	11.51
Length (mm)	11.51
Thickness (mm)	4.06
Pitch (mm)	1.27
Max Height (mm)	4.57
Mechanical Data	下载

参数化

Input Frequency(Max)	650 MHz
Input Level	LVPECL
Number of Outputs	9
Operating Temperature Range	-40 to 85 C
Output Frequency(Max)	650 MHz
Output Level	LVPECL
Package Group	PLCC
Package Size: mm2:W x L	28PLCC: 132 mm2: 11.51 x 11.51(PLCC) PKG
Rating	Catalog
VCC	3.3 V
VCC Out	3.3 V

生态计划

RoHS

Compliant

应用须知

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Using TI's CDC111 W/SLK2501 Serial Gigabit Transceiver for SONET, Ethernet
PDF, 72 Kb, 档案已发布: Oct 31, 2001
SONET/SDH and gigabit ethernet applications all have stringent timing requirements, which mandate the use of low-skew, low-jitter clock distribution. Texas Instruments has developed two products targeting these systems applications. The first product is the CDCVF111, a 1:9 low-skew, low-jitter differential LVPECL clock driver. The second is the SLK2501, a multirate (OC-48/24/12/3) serial gigabit t
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Using TI's CDC111/CDCVF111 W/ TLK3104SA Serial Transceiver for Gigabit Ethernet
PDF, 79 Kb, 档案已发布: Oct 31, 2001
This application report discusses jitter transfer of TI's CDC111/CDCVF111 clock drivers when driving TI's TLK3104 serial gigabit transceiver. This report summarizes worst case peak-to-peak and RMS jitter measurements taken at various points, as indicated in Figures 1 and 2. Two different clock sources are used to provide the reference clock signal for the clock drivers, and the output of each cloc
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Jitter Performance of TI's CDC111/CDCVF111
PDF, 149 Kb, 档案已发布: Oct 29, 2001
This application report discusses various jitter measurements of TI?s CDC111/CDCVF111 while being driven by three different clock sources (VCXOs). The data contained in this report shows that the CDC111/CDCVF111 does not add more than 3 ps of peak-to-peak jitter. Hence, the CDC111 and CDCVF111 are ideal for various SONET and Gigabit Ethernet applications where skew and jitter are of major concern.
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Output Jitter of CDC111/CDCVF111 in ASIC Networking Application
PDF, 361 Kb, 档案已发布: Nov 2, 2001
This report contains a number of peak-to-peak and cycle-to-cycle jitter measurements of TI?s CDC111 and CDCVF111 clock driver. In this ASIC event, both the CDC111/CDCVF111 clock drivers are used as a master clock distribution for the Gandalf Macro Family Testchip. Comprehensive jitter data as well as output signal levels were taken and thus are included for completeness.
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DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML
PDF, 135 Kb, 档案已发布: Feb 19, 2003
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AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C)
PDF, 417 Kb, 修订版: C, 档案已发布: Oct 17, 2007
This report provides a quick reference of ac-coupling techniques for interfacing between different logic levels. The four differential signaling levels found in this reportare low-voltage positive-referenced emitter coupled logic (LVPECL), low-voltage differential signals (LVDS), high-speed transceiver logic (HSTL), and current-modelogic (CML). From these four differential signaling levels, 16

模型线

系列: CDCVF111 (4)

CDCVF111FN CDCVF111FNG4 CDCVF111FNR CDCVF111FNRG4

制造商分类

Semiconductors > Clock and Timing > Clock Buffers > Differential