Datasheet Texas Instruments CDCM61004RHBT — 数据表

制造商Texas Instruments
系列CDCM61004
零件号CDCM61004RHBT
Datasheet Texas Instruments CDCM61004RHBT

1:4超低抖动晶体输入时钟发生器32-VQFN -40至85

数据表

CDCM61004 Four Output, Integrated VCO, Low-Jitter Clock Generator datasheet
PDF, 1.2 Mb, 修订版: H, 档案已发布: Jan 13, 2016
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin3232
Package TypeRHBRHB
Industry STD TermVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-N
Package QTY250250
CarrierSMALL T&RSMALL T&R
Device MarkingCDCM61004
Width (mm)55
Length (mm)55
Thickness (mm).9.9
Pitch (mm).5.5
Max Height (mm)11
Mechanical Data下载下载

参数化

Input LevelCrystal,LVCMOS
Number of Outputs4
Operating Temperature Range-40 to 85 C
Output Frequency(Max)683.264 MHz
Output Frequency(Min)43.75 MHz
Output LevelLVPECL, LVDS, LVCMOS
Package GroupVQFN
Package Size: mm2:W x L32VQFN: 25 mm2: 5 x 5(VQFN) PKG
ProgrammabilityPin configuration
Special Features3.3V Vcc/Vdd
VCC Core3.3 V
VCC Out3.3 V

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: CDCM6100XEVM
    CDCM61004/CDCM61002/CDCM61001 Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • Fibre Channel and SAN Clock Generation Using the CDCM6100x
    PDF, 322 Kb, 档案已发布: Feb 18, 2009
    This application report is a guide for using Texas Instruments CDCM6100x in a Fibre Channel application as a clock distributor and clock synthesizer along with measured jitter performance results.
  • Using LVCMOS Input to the CDCM6100x
    PDF, 66 Kb, 档案已发布: May 23, 2010
    This application report is a general guide for using LVCMOS inputs to the CDCM6100x series of ultra-low jitter clock generators from Texas Instruments. This document explains the basic connectivity of LVCMOS inputs to the CDCM6100x and recommends several methods for using the device that ensure proper operation.
  • Ethernet Clock Generation Using the CDCM6100x
    PDF, 454 Kb, 档案已发布: Feb 18, 2009
    This application report is a guide for using Texas Instruments CDCM6100x in an Ethernet LAN and WAN application as a clock distributor and clock synthesizer along with measured jitter performance results.
  • TI Powers Altera's Arria II GX FPGA Development Kit
    PDF, 596 Kb, 档案已发布: Sep 29, 2009

模型线

系列: CDCM61004 (3)

制造商分类

  • Semiconductors > Clock and Timing > Clock Generators > Low Jitter <1psec RMS