Datasheet Texas Instruments CDCLVD2106 — 数据表

制造商Texas Instruments
系列CDCLVD2106
Datasheet Texas Instruments CDCLVD2106

低抖动,双路1:6通用至LVDS缓冲器

数据表

Dual 1:6 Low Additive Jitter LVDS Buffer datasheet
PDF, 912 Kb, 修订版: B, 档案已发布: Jan 17, 2011
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状态

CDCLVD2106RHARCDCLVD2106RHAT
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoYes

打包

CDCLVD2106RHARCDCLVD2106RHAT
N12
Pin4040
Package TypeRHARHA
Industry STD TermVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-N
Package QTY2500250
CarrierLARGE T&RSMALL T&R
Device MarkingCDCLVDCDCLVD
Width (mm)66
Length (mm)66
Thickness (mm).9.9
Pitch (mm).5.5
Max Height (mm)11
Mechanical Data下载下载

参数化

Parameters / ModelsCDCLVD2106RHAR
CDCLVD2106RHAR
CDCLVD2106RHAT
CDCLVD2106RHAT
Additive RMS Jitter(Typ), fs171171
Input Frequency(Max), MHz800800
Input LevelLVCMOS,LVDS,LVPECLLVCMOS,LVDS,LVPECL
Number of Outputs1212
Operating Temperature Range, C-40 to 85-40 to 85
Output Frequency(Max), MHz800800
Output LevelLVDSLVDS
Package GroupVQFNVQFN
Package Size: mm2:W x L, PKG40VQFN: 36 mm2: 6 x 6(VQFN)40VQFN: 36 mm2: 6 x 6(VQFN)
RatingCatalogCatalog
VCC, V2.52.5
VCC Out, V2.52.5

生态计划

CDCLVD2106RHARCDCLVD2106RHAT
RoHSCompliantCompliant

模型线

系列: CDCLVD2106 (2)

制造商分类

  • Semiconductors> Clock and Timing> Clock Buffers> Differential