Datasheet Texas Instruments CDCF5801ADBQR — 数据表
| 制造商 | Texas Instruments |
| 系列 | CDCF5801A |
| 零件号 | CDCF5801ADBQR |
基于低抖动PLL的乘法器/分频器，可编程延迟线低至10ps以下24-SSOP -40至85
数据表
Clock Multiplier With Delay Control and Phase Alignment datasheet
PDF, 603 Kb, 档案已发布: Mar 15, 2006
从文件中提取
价格
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 24 |
| Package Type | DBQ |
| Industry STD Term | SSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2500 |
| Carrier | LARGE T&R |
| Device Marking | CDCF5801A |
| Width (mm) | 3.9 |
| Length (mm) | 8.65 |
| Thickness (mm) | 1.5 |
| Pitch (mm) | .64 |
| Max Height (mm) | 1.75 |
| Mechanical Data | 下载 |
参数化
| Input Level | HSTL,LVPECL,LVTTL |
| Number of Outputs | 1 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 280 MHz |
| Output Level | LVDS,LVPECL,LVTTL |
| Package Group | SSOP |
| Package Size: mm2:W x L | 24SSOP: 52 mm2: 6 x 8.65(SSOP) PKG |
| Programmability | Pin configuration |
| Special Features | Spread Spectrum Clocking (SSC),3.3V Vcc/Vdd |
| VCC Core | 3.3 V |
| VCC Out | 3.3 V |
生态计划
| RoHS | Compliant |
应用须知
- A General Guideline: How to Use the CDCF5801A for Phase Alignment/Adjustment (Rev. B)PDF, 129 Kb, 修订版: B, 档案已发布: Oct 21, 2005
Unlike regular PLLs, the CDCF5801 has an extra phase aligner. Using this extra phase aligner, the CDCF5801 can align two different clock phases, even with differentfrequencies. Examples of where phase alignment may be useful include:В· Applications where two clock buffers' outputs need to be alignedВ· Applications that require data synchronization with SERDESВ· Applications that require stati - Using Configurable Active Delay Elements in CDCF5801A Feedback LoopPDF, 43 Kb, 档案已发布: Sep 15, 2004
Using Configurable Active Delay Elements in CDCF5801 Feedback Loop
模型线
系列: CDCF5801A (4)
- CDCF5801ADBQ CDCF5801ADBQG4 CDCF5801ADBQR CDCF5801ADBQRG4
制造商分类
- Semiconductors > Clock and Timing > Clock Generators > General Purpose