Datasheet Texas Instruments CDCE937 — 数据表

制造商Texas Instruments
系列CDCE937
Datasheet Texas Instruments CDCE937

具有2.5V或3.3V LVCMOS输出的可编程3-PLL VCXO时钟合成器

数据表

CDCEx937 Flexible Low Power LVCMOS Clock Generator With SSC Support For EMI Reduction datasheet
PDF, 1.2 Mb, 修订版: G, 档案已发布: Oct 10, 2016
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价格

状态

CDCE937PWCDCE937PWG4CDCE937PWRCDCE937PWRG4HPA00406PWR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYesNoNoNo

打包

CDCE937PWCDCE937PWG4CDCE937PWRCDCE937PWRG4HPA00406PWR
N12345
Pin2020202020
Package TypePWPWPWPWPW
Industry STD TermTSSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY7070200020002000
CarrierTUBETUBELARGE T&RLARGE T&RLARGE T&R
Device MarkingCDCE937CDCE937CDCE937CDCE937CDCE937
Width (mm)4.44.44.44.44.4
Length (mm)6.56.56.56.56.5
Thickness (mm)11111
Pitch (mm).65.65.65.65.65
Max Height (mm)1.21.21.21.21.2
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参数化

Parameters / ModelsCDCE937PW
CDCE937PW
CDCE937PWG4
CDCE937PWG4
CDCE937PWR
CDCE937PWR
CDCE937PWRG4
CDCE937PWRG4
HPA00406PWR
HPA00406PWR
Divider RatioUniversalUniversalUniversalUniversalUniversal
FunctionClock SynthesizerClock SynthesizerClock SynthesizerClock SynthesizerClock Synthesizer
Input LevelCrystal,LVCMOSCrystal,LVCMOSCrystal,LVCMOSCrystal,LVCMOSCrystal,LVCMOS
Jitter-Peak to Peak(P-P) or Cycle to Cycle, C-C60 ps60 ps60 ps60 ps60 ps
Number of Outputs77777
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Frequency(Max), MHz230230230230230
Output LevelLVCMOSLVCMOSLVCMOSLVCMOSLVCMOS
Output Skew, ps150150150150150
Package GroupTSSOPTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
ProgrammabilityEEPROMEEPROMEEPROMEEPROMEEPROM
RatingCatalogCatalogCatalogCatalogCatalog
Special FeaturesIntegrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)Integrated EEPROM,Multiplier/Divider,Spread Spectrum Clocking (SSC)
VCC, V1.81.81.81.81.8
VCC Core, V1.81.81.81.81.8
VCC Out, V2.5,3.32.5,3.32.5,3.32.5,3.32.5,3.3

生态计划

CDCE937PWCDCE937PWG4CDCE937PWRCDCE937PWRG4HPA00406PWR
RoHSCompliantCompliantCompliantCompliantCompliant

应用须知

  • General I2C / EEPROM usage for the CDCE(L)9xx family
    PDF, 40 Kb, 档案已发布: Jan 26, 2010
  • VCXO Application Guideline for CDCE(L)9xx Family (Rev. A)
    PDF, 107 Kb, 修订版: A, 档案已发布: Apr 23, 2012
  • Practical consideration on choosing a crystal for CDCE(L)9xx family
    PDF, 60 Kb, 档案已发布: Mar 24, 2008
  • Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913
    PDF, 297 Kb, 档案已发布: Sep 23, 2009
    This document presents a method to smoothly change frequency by IВІCв„ў protocol on Texas Instruments CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 Clock Synthesizers, thus avoiding unnecessary intermediate frequencies. It also includes a code example to generate the IВІC protocol for the CDCE(L)9xx with the TMS320C645x.
  • Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency
    PDF, 860 Kb, 档案已发布: Mar 31, 2008
    Generating a high-frequency system clock Fs (128fs to 768fs) from a low-frequency sampling clock fs (10 kHz to 200 kHz) is challenging, while attempting to maintain low phase jitter. A traditional phase-lock loop (PLL) can do the frequency translation, but the added phase jitter prevents the generated system clock signal from effectively driving high-performance audio data converters. This applica
  • Troubleshooting I2C Bus Protocol
    PDF, 184 Kb, 档案已发布: Oct 19, 2009
    When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

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制造商分类

  • Semiconductors> Clock and Timing> Clock Generators> Spread-Spectrum Clocks