Datasheet Texas Instruments CDC536DBR — 数据表

制造商Texas Instruments
系列CDC536
零件号CDC536DBR
Datasheet Texas Instruments CDC536DBR

具有1 / 2x,1x和2x频率选项的3.3V PLL时钟驱动器28-SSOP

数据表

CDC536: 3.3-V PLL Clock Driver With 3-State Outputs datasheet
PDF, 322 Kb, 修订版: G, 档案已发布: Jul 8, 2004
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin28
Package TypeDB
Industry STD TermSSOP
JEDEC CodeR-PDSO-G
Package QTY2000
CarrierLARGE T&R
Device MarkingCDC536
Width (mm)5.3
Length (mm)10.2
Thickness (mm)1.95
Pitch (mm).65
Max Height (mm)2
Mechanical Data下载

参数化

Absolute Jitter (Peak-to-Peak Cycle or Period Jitter)200 ps
Number of Outputs6
Operating Frequency Range(Max)100 MHz
Operating Frequency Range(Min)25 MHz
Package GroupSSOP
Package Size: mm2:W x L28SSOP: 80 mm2: 7.8 x 10.2(SSOP) PKG
RatingCatalog
VCC3.3 V
t(phase error)500 ps
tsk(o)500 ps

生态计划

RoHSCompliant

应用须知

  • Application and Design Considerations for CDC5xx Phase-Lock Loop Clock Drivers
    PDF, 101 Kb, 档案已发布: Apr 1, 1996
    Today?s high-speed system designs require stringent propagation and skew parameters to maintain desired system performance. TI developed the CDC5XX platform of PLL clock drivers to meet the need for high-performance clock system components. This document describes the features and functions of the CDC5XX and discusses design considerations and configurations for the CDC586, CDC582, and CDC2582 clo

模型线

系列: CDC536 (4)

制造商分类

  • Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers