Datasheet Texas Instruments CDC509 — 数据表

制造商Texas Instruments
系列CDC509
Datasheet Texas Instruments CDC509

3.3V锁相环时钟驱动器

数据表

CDC509: 3.3-V Phase-Lock Loop Clock Driver datasheet
PDF, 612 Kb, 修订版: C, 档案已发布: Dec 2, 2004
从文件中提取

价格

状态

CDC509PWRCDC509PWRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYes

打包

CDC509PWRCDC509PWRG4
N12
Pin2424
Package TypePWPW
Industry STD TermTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-G
Package QTY20002000
CarrierLARGE T&RLARGE T&R
Device MarkingCK509CK509
Width (mm)4.44.4
Length (mm)7.87.8
Thickness (mm)11
Pitch (mm).65.65
Max Height (mm)1.21.2
Mechanical Data下载下载

参数化

Parameters / ModelsCDC509PWR
CDC509PWR
CDC509PWRG4
CDC509PWRG4
Absolute Jitter (Peak-to-Peak Cycle or Period Jitter), ps200200
Number of Outputs99
Operating Frequency Range(Max), MHz125125
Operating Frequency Range(Min), MHz2525
Operating Temperature Range, C0 to 700 to 70
Package GroupTSSOPTSSOP
Package Size: mm2:W x L, PKG24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)
RatingCatalogCatalog
VCC, V3.33.3
t(phase error), ps480480
tsk(o), ps200200

生态计划

CDC509PWRCDC509PWRG4
RoHSCompliantCompliant

应用须知

  • High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)
    PDF, 109 Kb, 修订版: A, 档案已发布: Sep 23, 1998
    The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo

模型线

系列: CDC509 (2)

制造商分类

  • Semiconductors> Clock and Timing> Clock Buffers> Zero Delay Buffers