Datasheet Texas Instruments CDC3S04 — 数据表

制造商	Texas Instruments
系列	CDC3S04

数据表

价格

状态

打包

参数化

Parameters / Models	CDC3S04YFFR
Additive RMS Jitter(Typ), fs	300
Input Frequency(Max), MHz	52
Input Level	SINE
Number of Outputs	4
Operating Temperature Range, C	-40 to 85
Output Frequency(Max), MHz	52
Output Level	SINE
Package Group	DSBGA
Package Size: mm2:W x L, PKG	See datasheet (DSBGA)
Rating	Catalog
VCC Out, V	1.8

生态计划

应用须知

• 下载
  Using the CDC3S04
  PDF, 110 Kb, 档案已发布: Apr 18, 2010
  When designing a single-ended clock tree, a system designer can choose between two commonly-used waveform types: rectangular or sinusoidal. This application note gives a short overview of both signal types and shows the advantages and disadvantages of each using the CDC3S04 quad sine-wave clock buffer with an integrated low-dropout regulator (LDO). Additionally, the clipped sinusoidal waveform is
• 下载
  Power Supply Rejection to Noise in Sinusoidal Clock Buffers: CDC3S04 (Rev. A)
  PDF, 12.8 Mb, 修订版: A, 档案已发布: Jun 21, 2010
  This application report is an overview on how power supply noise affects some key specifications of the CDC3S04 sine wave buffer. The ripple in the power supply induces additional harmonics in the frequency spectrum and spurs in the phase noise plot, thus degrading the overall jitter and EMI performance. Decoupling capacitors significantly minimize these effects. This document provides guidelines

模型线

制造商分类

• Semiconductors> Clock and Timing> Clock Buffers> Single-Ended