Datasheet Texas Instruments CDC208DWG4 — 数据表
| 制造商 | Texas Instruments |
| 系列 | CDC208 |
| 零件号 | CDC208DWG4 |
5V双1至4时钟驱动器20-SOIC
数据表
Dual 1-Line To 4-Line Clock Drivers With 3-State Outputs datasheet
PDF, 1.1 Mb, 修订版: F, 档案已发布: Oct 28, 1998
从文件中提取
状态
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
打包
| Pin | 20 |
| Package Type | DW |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | CDC208 |
| Width (mm) | 7.5 |
| Length (mm) | 12.8 |
| Thickness (mm) | 2.35 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 2.65 |
| Mechanical Data | 下载 |
参数化
| Input Frequency(Max) | 60 MHz |
| Input Level | TTL |
| Number of Outputs | 8 |
| Operating Temperature Range | -40 to 85 C |
| Output Frequency(Max) | 60 MHz |
| Output Level | CMOS |
| Package Group | SOIC |
| Package Size: mm2:W x L | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) PKG |
| Rating | Catalog |
| VCC Out | 5 V |
生态计划
| RoHS | Compliant |
应用须知
- Minimizing Clock Driver Output Skew Using Ganged OutputsPDF, 53 Kb, 档案已发布: Jan 1, 1994
This document helps designers use existing clock-driver products to drive large loads while maintaining a minimum amount of skew between the device outputs. The emphasis of this document is using parallel or ganged outputs to drive loads. A performance evaluation of the CDC201 is provided.
模型线
系列: CDC208 (8)
- CDC208DW CDC208DWG4 CDC208DWR CDC208DWRG4 CDC208NS CDC208NSG4 CDC208NSR CDC208NSRG4
制造商分类
- Semiconductors > Clock and Timing > Clock Buffers > Single-Ended