[ /Title
(CD74
HC297
,
CD74
HCT29
7)
/Subject
(HighSpeed
CMOS
Logic
Digital
PhaseLocked CD54HC297, CD74HC297,
CD74HCT297
Data sheet acquired from Harris Semiconductor
SCHS177B High-Speed CMOS Logic
Digital Phase-Locked Loop November 1997 -Revised May 2003 Features Description Digital Design Avoids Analog Compensation Errors The ’HC297 and CD74HCT297 are high-speed silicon gate
CMOS devices that are pin-compatible with low power Schottky TTL (LSTTL). Easily Cascadable for Higher Order Loops Useful Frequency Range
-K-Clock . .DC to 55MHz (Typ)
-I/D-Clock DC to 35MHz (Typ) These devices are designed to provide a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop applications. They contain all the necessary circuits, with the
exception of the divide-by-N counter, to build first-order
phase-locked-loops. Dynamically Variable Bandwidth Very Narrow Bandwidth Attainable Both EXCLUSIVE-OR (XORPD) and edge-controlled phase
detectors (ECPD) are provided for maximum flexibility. The …
