Datasheet Texas Instruments CD74ACT10 — 数据表

制造商Texas Instruments
系列CD74ACT10
Datasheet Texas Instruments CD74ACT10

三路3输入与非门

数据表

CD74ACT10 datasheet
PDF, 798 Kb, 档案已发布: Nov 4, 2002
从文件中提取

价格

状态

CD74ACT10ECD74ACT10MCD74ACT10M96CD74ACT10M96G4CD74ACT10MG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNo

打包

CD74ACT10ECD74ACT10MCD74ACT10M96CD74ACT10M96G4CD74ACT10MG4
N12345
Pin1414141414
Package TypeNDDDD
Industry STD TermPDIPSOICSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY25502500250050
CarrierTUBETUBELARGE T&RLARGE T&RTUBE
Device MarkingCD74ACT10EACT10MACT10MACT10MACT10M
Width (mm)6.353.913.913.913.91
Length (mm)19.38.658.658.658.65
Thickness (mm)3.91.581.581.581.58
Pitch (mm)2.541.271.271.271.27
Max Height (mm)5.081.751.751.751.75
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参数化

Parameters / ModelsCD74ACT10E
CD74ACT10E
CD74ACT10M
CD74ACT10M
CD74ACT10M96
CD74ACT10M96
CD74ACT10M96G4
CD74ACT10M96G4
CD74ACT10MG4
CD74ACT10MG4
Bits33333
F @ Nom Voltage(Max), Mhz9090909090
ICC @ Nom Voltage(Max), mA0.040.040.040.040.04
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-24
Package GroupPDIPSOICSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)14SOIC: 52 mm2: 6 x 8.65(SOIC)
RatingCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNo
Technology FamilyACTACTACTACTACT
VCC(Max), V5.55.55.55.55.5
VCC(Min), V4.54.54.54.54.5
Voltage(Nom), V55555
tpd @ Nom Voltage(Max), ns12.312.312.312.312.3

生态计划

CD74ACT10ECD74ACT10MCD74ACT10M96CD74ACT10M96G4CD74ACT10MG4
RoHSCompliantCompliantCompliantCompliantCompliant
Pb FreeYes

应用须知

  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, 修订版: A, 档案已发布: Jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, 档案已发布: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

模型线

制造商分类

  • Semiconductors> Logic> Gate> NAND Gate