Datasheet Texas Instruments CD74AC273 — 数据表

制造商Texas Instruments
系列CD74AC273
Datasheet Texas Instruments CD74AC273

具有复位功能的八路D类触发器

数据表

Octal D Flip-Flop with Reset datasheet
PDF, 944 Kb, 修订版: B, 档案已发布: Jul 1, 2002
从文件中提取

价格

状态

CD74AC273ECD74AC273EE4CD74AC273MCD74AC273M96CD74AC273M96E4CD74AC273M96G4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNo

打包

CD74AC273ECD74AC273EE4CD74AC273MCD74AC273M96CD74AC273M96E4CD74AC273M96G4
N123456
Pin202020202020
Package TypeNNDWDWDWDW
Industry STD TermPDIPPDIPSOICSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY202025200020002000
CarrierTUBETUBETUBELARGE T&RLARGE T&RLARGE T&R
Device MarkingCD74AC273ECD74AC273EAC273MAC273MAC273MAC273M
Width (mm)6.356.357.57.57.57.5
Length (mm)24.3324.3312.812.812.812.8
Thickness (mm)4.574.572.352.352.352.35
Pitch (mm)2.542.541.271.271.271.27
Max Height (mm)5.085.082.652.652.652.65
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参数化

Parameters / ModelsCD74AC273E
CD74AC273E
CD74AC273EE4
CD74AC273EE4
CD74AC273M
CD74AC273M
CD74AC273M96
CD74AC273M96
CD74AC273M96E4
CD74AC273M96E4
CD74AC273M96G4
CD74AC273M96G4
3-State OutputNoNoNoNoNoNo
Bits888888
F @ Nom Voltage(Max), Mhz100100100100100100
ICC @ Nom Voltage(Max), mA0.080.080.080.080.080.08
Operating Temperature Range, C-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125-55 to 125
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-2424/-24
Package GroupPDIPPDIPSOICSOICSOICSOIC
Package Size: mm2:W x L, PKGSee datasheet (PDIP)See datasheet (PDIP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNo
Technology FamilyACACACACACAC
VCC(Max), V5.55.55.55.55.55.5
VCC(Min), V1.51.51.51.51.51.5
Voltage(Nom), V1.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,51.5,3.3,5
tpd @ Nom Voltage(Max), ns154,17.2,12.3154,17.2,12.3154,17.2,12.3154,17.2,12.3154,17.2,12.3154,17.2,12.3

生态计划

CD74AC273ECD74AC273EE4CD74AC273MCD74AC273M96CD74AC273M96E4CD74AC273M96G4
RoHSCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYesYes

应用须知

  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, 档案已发布: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

模型线

制造商分类

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop