Datasheet Texas Instruments ADS901 — 数据表

制造商Texas Instruments
系列ADS901
Datasheet Texas Instruments ADS901

10位20MSPS模数转换器(ADC)

数据表

ADS901: SpeedPlus? 10-Bit, 20MHz, +3V Supply Analog-To-Digital Converter datasheet
PDF, 254 Kb, 修订版: A, 档案已发布: Feb 23, 2001
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价格

状态

ADS901E
Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

ADS901E
N1
Pin28
Package TypeDB
Industry STD TermSSOP
JEDEC CodeR-PDSO-G
Package QTY50
CarrierTUBE
Device MarkingADS901E
Width (mm)5.3
Length (mm)10.2
Thickness (mm)1.95
Pitch (mm).65
Max Height (mm)2
Mechanical Data下载

参数化

Parameters / ModelsADS901E
ADS901E
# Input Channels1
Analog Input BW, MHz100
ArchitecturePipeline
DNL(Max), +/-LSB1
DNL(Typ), +/-LSB0.8
ENOB, Bits8
INL(Max), +/-LSB3.5
INL(Typ), +/-LSB3.5
Input BufferNo
Input Range, Vp-p1,2
InterfaceParallel CMOS
Operating Temperature Range, C-40 to 85
Package GroupSSOP
Package Size: mm2:W x L, PKG28SSOP: 80 mm2: 7.8 x 10.2(SSOP)
Power Consumption(Typ), mW49
RatingCatalog
Reference ModeExt
Resolution, Bits10
SFDR, dB49
SINAD, dB50
SNR, dB53
Sample Rate(Max), MSPS20

生态计划

ADS901E
RoHSCompliant

应用须知

  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

模型线

系列: ADS901 (1)

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)