Datasheet Texas Instruments ADS830 — 数据表

制造商Texas Instruments
系列ADS830
Datasheet Texas Instruments ADS830

8位,60MSPS模数转换器(ADC)

数据表

ADS830: SpeedPlus? 8-Bit, 60MHz Sampling Analog-To-Digital Converter datasheet
PDF, 554 Kb, 修订版: A, 档案已发布: Feb 23, 2001
从文件中提取
ADS830: SpeedPlus? 8-Bit, 60MHz Sampling Analog-To-Digital Converter (Rev. A)
PDF, 557 Kb, 修订版: A, 档案已发布: Feb 23, 2001

价格

状态

ADS830EADS830E/2K5ADS830EG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYesNo

打包

ADS830EADS830E/2K5ADS830EG4
N123
Pin202020
Package TypeDBQDBQDBQ
Industry STD TermSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY50250050
CarrierTUBELARGE T&RTUBE
Device MarkingADS830EADS830EADS830E
Width (mm)3.93.93.9
Length (mm)8.658.658.65
Thickness (mm)1.51.51.5
Pitch (mm).64.64.64
Max Height (mm)1.751.751.75
Mechanical Data下载下载下载

参数化

Parameters / ModelsADS830E
ADS830E
ADS830E/2K5
ADS830E/2K5
ADS830EG4
ADS830EG4
# Input Channels111
Analog Input BW, MHz300300
Analog Input BW(MHz)300
Approx. Price (US$)3.28 | 1ku
ArchitecturePipelinePipelinePipeline
DNL(Max), +/-LSB11
DNL(Max)(+/-LSB)1
DNL(Typ), +/-LSB0.10.1
ENOB, Bits7.77.7
ENOB(Bits)7.7
INL(Max), +/-LSB1.51.5
INL(Max)(+/-LSB)1.5
INL(Typ), +/-LSB0.30.3
Input BufferNoNo
Input Range1,21,21V / 2V (p-p)
InterfaceParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Package GroupSSOPSSOPSSOP
Package Size(mm2=WxL)20SSOP: 52 mm2: 6 x 8.65
Package Size: mm2:W x L, PKG20SSOP: 52 mm2: 6 x 8.65(SSOP)20SSOP: 52 mm2: 6 x 8.65(SSOP)
Power Consumption(Typ), mW215215
Power Consumption(Typ)(mW)215
RatingCatalogCatalogCatalog
Reference ModeExt,IntExt,IntInt
Ext
Resolution, Bits88
Resolution(Bits)8
SFDR, dB6565
SFDR(dB)65
SINAD, dB4848
SINAD(dB)48
SNR, dB49.549.5
SNR(dB)49.5
Sample Rate (max)(SPS)60MSPS
Sample Rate(Max), MSPS6060

生态计划

ADS830EADS830E/2K5ADS830EG4
RoHSCompliantCompliantCompliant
Pb FreeYes

应用须知

  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015

模型线

系列: ADS830 (3)

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)