Datasheet Texas Instruments ADS826 — 数据表

制造商Texas Instruments
系列ADS826
Datasheet Texas Instruments ADS826

10位,60MSPS模数转换器(ADC)

数据表

ADS823, ADS826: 10-Bit, 60MHz Sampling Analog-To-Digital Converter (Rev. B)
PDF, 873 Kb, 修订版: B, 档案已发布: Jun 28, 2002
ADS823, ADS826: 10-Bit, 60MHz Sampling Analog-To-Digital Converter datasheet
PDF, 869 Kb, 修订版: B, 档案已发布: Jun 28, 2002
从文件中提取

价格

状态

ADS826EADS826E/1KADS826EG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

打包

ADS826EADS826E/1KADS826EG4
N123
Pin282828
Package TypeDBDBDB
Industry STD TermSSOPSSOPSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY50100050
CarrierTUBELARGE T&RTUBE
Device MarkingADS826EADS826EADS826E
Width (mm)5.35.35.3
Length (mm)10.210.210.2
Thickness (mm)1.951.951.95
Pitch (mm).65.65.65
Max Height (mm)222
Mechanical Data下载下载下载

参数化

Parameters / ModelsADS826E
ADS826E
ADS826E/1K
ADS826E/1K
ADS826EG4
ADS826EG4
# Input Channels111
Analog Input BW, MHz300300
Analog Input BW(MHz)300
Approx. Price (US$)12.69 | 1ku
ArchitecturePipelinePipelinePipeline
DNL(Max), +/-LSB11
DNL(Max)(+/-LSB)1
DNL(Typ), +/-LSB0.250.25
ENOB, Bits9.59.5
ENOB(Bits)9.5
INL(Max), +/-LSB22
INL(Max)(+/-LSB)2
INL(Typ), +/-LSB0.50.5
Input BufferNoNo
Input Range1,21,21V / 2V (p-p)
InterfaceParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Package GroupSSOPSSOPSSOP
Package Size(mm2=WxL)28SSOP: 80 mm2: 7.8 x 10.2
Package Size: mm2:W x L, PKG28SSOP: 80 mm2: 7.8 x 10.2(SSOP)28SSOP: 80 mm2: 7.8 x 10.2(SSOP)
Power Consumption(Typ), mW295295
Power Consumption(Typ)(mW)295
RatingCatalogCatalogCatalog
Reference ModeExt,IntExt,IntInt
Ext
Resolution, Bits1010
Resolution(Bits)10
SFDR, dB7373
SFDR(dB)73
SINAD, dB5858
SINAD(dB)58
SNR, dB5959
SNR(dB)59
Sample Rate (max)(SPS)60MSPS
Sample Rate(Max), MSPS6060

生态计划

ADS826EADS826E/1KADS826EG4
RoHSCompliantCompliantCompliant
Pb FreeYes

应用须知

  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • ADS82x ADC with non-uniform sampling clock
    PDF, 234 Kb, 档案已发布: Feb 28, 2005
  • RLC Filter Design for ADC Interface Applications (Rev. A)
    PDF, 299 Kb, 修订版: A, 档案已发布: May 13, 2015
    As high performance Analog-to-Digital Converters (ADCs) continue to improve in their performance, the last stage interface from the final amplifier into the converter inputs becomes a critical element in the system design if the full converter dynamic range is desired. This application note describes the performance and design equations for a simple passive 2nd-order filter used successfully in AD
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.

模型线

系列: ADS826 (3)

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)