Datasheet Texas Instruments ADS801 — 数据表

制造商Texas Instruments
系列ADS801
Datasheet Texas Instruments ADS801

12位,25 MSPS ADC SE /差分输入内部基准,引脚兼容ADS800 / 2

数据表

12-Bit, 25MHz Sampling Analog-To-Digital Converter datasheet
PDF, 358 Kb, 修订版: B, 档案已发布: Feb 14, 2005
从文件中提取
12-Bit, 25MHz Sampling Analog-To-Digital Converter (Rev. B)
PDF, 384 Kb, 修订版: B, 档案已发布: Feb 14, 2005

价格

状态

ADS801EADS801E/1KADS801UADS801UG4
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNo

打包

ADS801EADS801E/1KADS801UADS801UG4
N1234
Pin28282828
Package TypeDBDBDWDW
Industry STD TermSSOPSSOPSOICSOIC
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)5.35.37.57.5
Length (mm)10.210.217.917.9
Thickness (mm)1.951.952.352.35
Pitch (mm).65.651.271.27
Max Height (mm)222.652.65
Mechanical Data下载下载下载下载
Package QTY2020
CarrierTUBETUBE
Device MarkingADS801UADS801U

参数化

Parameters / ModelsADS801E
ADS801E
ADS801E/1K
ADS801E/1K
ADS801U
ADS801U
ADS801UG4
ADS801UG4
# Input Channels1111
Analog Input BW, MHz65
Analog Input BW(MHz)656565
Approx. Price (US$)19.26 | 1ku19.26 | 1ku19.26 | 1ku
ArchitecturePipelinePipelinePipelinePipeline
DNL(Max), +/-LSB0.4
DNL(Max)(+/-LSB)0.40.40.4
DNL(Typ), +/-LSB0.4
ENOB, Bits10.3
ENOB(Bits)10.310.310.3
INL(Max), +/-LSB1.7
INL(Max)(+/-LSB)1.71.71.7
INL(Typ), +/-LSB1.7
Input BufferNoNoNo
Input Range2V (p-p)2V (p-p)22V (p-p)
InterfaceParallel CMOSParallel CMOSParallel CMOSParallel CMOS
Operating Temperature Range, C-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85-40 to 85
Package GroupSOICSOICSOICSOIC
Package Size(mm2=WxL)28SOIC: 184 mm2: 10.3 x 17.9
Package Size: mm2:W x L, PKG28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Package Size: mm2:W x L (PKG)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Power Consumption(Typ), mW270
Power Consumption(Typ)(mW)270270270
RatingCatalogCatalogCatalogCatalog
Reference ModeExt
Int
Ext
Int
Ext,IntInt
Ext
Resolution, Bits12
Resolution(Bits)121212
SFDR, dB61
SFDR(dB)616161
SINAD, dB66
SINAD(dB)666666
SNR, dB64
SNR(dB)646464
Sample Rate (max)(SPS)25MSPS
Sample Rate(Max), MSPS25
Sample Rate(Max)(MSPS)2525

生态计划

ADS801EADS801E/1KADS801UADS801UG4
RoHSNot CompliantNot CompliantCompliantCompliant
Pb FreeNoYesNo

应用须知

  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
  • What Designers Should Know About Data Converter Drift
    PDF, 95 Kb, 档案已发布: Oct 2, 2000
    Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.
  • Interleaving Analog-to-Digital Converters
    PDF, 64 Kb, 档案已发布: Oct 2, 2000
    It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error.
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527, which is capable of sampling up to 210 MSPS. To realize the full potential of thes
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
    AB-082 Principles of Data Acquisition and Conversion
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
    AB-084 Analog-to-Digital Grounding Practices Affect System Performance
  • Interleaving Analog-to-Digital Converters
    PDF, 64 Kb, 档案已发布: Oct 2, 2000
    It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration s
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (ΔΣ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specificati
  • What Designers Should Know About Data Converter Drift
    PDF, 95 Kb, 档案已发布: Oct 2, 2000
    Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its oper

模型线

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)