Datasheet Texas Instruments ADS774 — 数据表

制造商Texas Instruments
系列ADS774
Datasheet Texas Instruments ADS774

微处理器兼容的采样CMOS A / D转换器

数据表

Microprocessor-Compatible Sampling CMOS A/D Converter
PDF, 744 Kb, 档案已发布: Sep 27, 2000
Microprocessor-Compatible Sampling CMOS A/D Converter datasheet
PDF, 935 Kb, 档案已发布: Sep 27, 2000
从文件中提取

价格

状态

ADS774JPADS774JPG4ADS774JUADS774JU/1KADS774JUE4ADS774KUADS774KU/1KADS774KU/1KE4ADS774KUE4
Lifecycle StatusLifebuy (Manufacturer has announced that the device will be discontinued, and a lifetime-buy period is in effect)Lifebuy (Manufacturer has announced that the device will be discontinued, and a lifetime-buy period is in effect)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoYesNoNoNoNoNoNo

打包

ADS774JPADS774JPG4ADS774JUADS774JU/1KADS774JUE4ADS774KUADS774KU/1KADS774KU/1KE4ADS774KUE4
N123456789
Pin282828282828282828
Package TypeNTDNTDDWDWDWDWDWDWDW
Industry STD TermPDIPPDIPSOICSOICSOICSOICSOICSOICSOIC
JEDEC CodeR-PDIP-TR-PDIP-TR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY131320100020201000100020
CarrierTUBETUBETUBELARGE T&RTUBETUBELARGE T&RLARGE T&RTUBE
Device MarkingADS774JPADS774JPADS774JUADS774JUADS774JUADS774KUADS774KUADS774KUADS774KU
Width (mm)13.52513.5257.57.57.57.57.57.57.5
Length (mm)37.437.417.917.917.917.917.917.917.9
Thickness (mm)4.074.072.352.352.352.352.352.352.35
Pitch (mm)2.542.541.271.271.271.271.271.271.27
Max Height (mm)6.356.352.652.652.652.652.652.652.65
Mechanical Data下载下载下载下载下载下载下载下载下载

参数化

Parameters / ModelsADS774JP
ADS774JP
ADS774JPG4
ADS774JPG4
ADS774JU
ADS774JU
ADS774JU/1K
ADS774JU/1K
ADS774JUE4
ADS774JUE4
ADS774KU
ADS774KU
ADS774KU/1K
ADS774KU/1K
ADS774KU/1KE4
ADS774KU/1KE4
ADS774KUE4
ADS774KUE4
# Input Channels111111111
Analog Voltage AV/DD(Max)(V)5.55.5
Analog Voltage AV/DD(Min)(V)4.54.5
Analog Voltage AVDD(Max), V5.55.55.55.55.55.55.5
Analog Voltage AVDD(Min), V4.54.54.54.54.54.54.5
Approx. Price (US$)20.08 | 1ku20.08 | 1ku
ArchitectureSARSARSARSARSARSARSARSARSAR
Digital Supply(Max), V5.55.55.55.55.55.55.5
Digital Supply(Max)(V)5.55.5
Digital Supply(Min), V4.54.54.54.54.54.54.5
Digital Supply(Min)(V)4.54.5
INL(Max), +/-LSB0.50.50.50.50.50.50.5
INL(Max)(+/-LSB)0.50.5
Input Range(Max), V10101010101010
Input Range(Max)(V)1010
Input Range(Min), V-10-10-10-10-10-10-10
Input Range(Min)(V)-10-10
Input TypeSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-EndedSingle-Ended
Integrated FeaturesN/AN/AN/AN/AN/AN/AN/A
InterfaceParallelParallelParallelParallelParallelParallelParallelParallelParallel
Multi-Channel ConfigurationN/AN/AN/AN/AN/AN/AN/A
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Package GroupSOICSOICSOICSOICSOICSOICSOICSOICSOIC
Package Size(mm2=WxL)28SOIC: 184 mm2: 10.3 x 17.928SOIC: 184 mm2: 10.3 x 17.9
Package Size: mm2:W x L, PKG28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Power Consumption(Typ), mW75757575757575
Power Consumption(Typ)(mW)7575
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Reference ModeExt
Int
Ext
Int
Ext,IntExt,IntExt,IntExt,IntExt,IntExt,IntExt,Int
Resolution, Bits12121212121212
Resolution(Bits)1212
SINAD, dBN/AN/AN/AN/AN/AN/AN/A
SINAD(dB)7171
SNR, dB72727272727272
SNR(dB)7272
Sample Rate (max), SPS117kSPS117kSPS117kSPS117kSPS117kSPS117kSPS117kSPS
Sample Rate (max)(SPS)125kSPS125kSPS
Sample Rate(Max), MSPS0.1170.1170.1170.1170.1170.1170.117
THD(Typ), dB-77-77-77-77-77-77-77
THD(Typ)(dB)-77-77

生态计划

ADS774JPADS774JPG4ADS774JUADS774JU/1KADS774JUE4ADS774KUADS774KU/1KADS774KU/1KE4ADS774KUE4
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYesYes

应用须知

  • CDAC Architecture Gives ADC574 Pinout /Sampling, Low Power, New Input Ranges
    PDF, 54 Kb, 档案已发布: Sep 27, 2000
    This application note compares basic current-mode successive approximation A/Ds with CDAC-based architectures, and shows how adding a resistor divider network to the CDAC input permits the Burr-Brown ADS574 and ADS774 to fit existing ADC574 sockets. It then goes on to descibe some new analog input voltage ranges available on these parts due to the resistor network and CDAC approach.
  • Complete Temp Data Acquisition System From a Single +5V Supply
    PDF, 68 Kb, 档案已发布: Oct 2, 2000
    The CMOS ADS574 and ADS774 are drop-in replacements for industry standard ADC574 analog-to-digital converter, offering lower power and the capability to operate from a single +5V supply. The switched capacitor array architecture (CDAC), with the input resistor divider network to provide ADC574 input ranges, also allow the new parts to handle additional input ranges, including a 0V to 5V range. Thi
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
  • Determining Minimum Acquisition Times for SAR ADCs, part 2
    PDF, 215 Kb, 档案已发布: Mar 17, 2011
    The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
  • CDAC Architecture Gives ADC574 Pinout /Sampling, Low Power, New Input Ranges
    PDF, 54 Kb, 档案已发布: Sep 27, 2000
    This application note compares basic current-mode successive approximation A/Ds with CDAC-based architectures, and shows how adding a resistor divider network to the CDAC input permits the Burr-Brown
  • Complete Temp Data Acquisition System From a Single +5V Supply
    PDF, 68 Kb, 档案已发布: Oct 2, 2000
    The CMOS ADS574 and ADS774 are drop-in replacements for industry standard ADC574 analog-to-digital converter, offering lower power and the capability to operate from a single +5V supply. The switched
  • Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
    PDF, 227 Kb, 修订版: A, 档案已发布: Nov 10, 2010
    This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
    AB-084 Analog-to-Digital Grounding Practices Affect System Performance
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (ΔΣ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specificati
  • Interleaving Analog-to-Digital Converters
    PDF, 64 Kb, 档案已发布: Oct 2, 2000
    It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration s
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
    AB-082 Principles of Data Acquisition and Conversion
  • What Designers Should Know About Data Converter Drift
    PDF, 95 Kb, 档案已发布: Oct 2, 2000
    Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its oper

模型线

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> Precision ADCs (<=10MSPS)