Datasheet Texas Instruments ADS62P28 — 数据表

制造商Texas Instruments
系列ADS62P28
Datasheet Texas Instruments ADS62P28

双通道,12位,210MSPS模数转换器(ADC)

数据表

Dual Channel 14-/12-Bit, 250/210 MSPS ADC with DDR LVDS & Parallel CMOS Outputs datasheet
PDF, 2.4 Mb, 修订版: B, 档案已发布: Jan 4, 2011
从文件中提取

价格

状态

ADS62P28IRGCRADS62P28IRGCT
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNo

打包

ADS62P28IRGCRADS62P28IRGCT
N12
Pin6464
Package TypeRGCRGC
Industry STD TermVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-N
Package QTY2000250
CarrierLARGE T&RSMALL T&R
Device MarkingAZ62P28AZ62P28
Width (mm)99
Length (mm)99
Thickness (mm).88.88
Pitch (mm).5.5
Max Height (mm)11
Mechanical Data下载下载

参数化

Parameters / ModelsADS62P28IRGCR
ADS62P28IRGCR
ADS62P28IRGCT
ADS62P28IRGCT
# Input Channels22
Analog Input BW, MHz700700
ArchitecturePipelinePipeline
DNL(Max), +/-LSB1.31.3
DNL(Typ), +/-LSB0.20.2
ENOB, Bits1111
INL(Max), +/-LSB55
INL(Typ), +/-LSB11
Input BufferNoNo
Input Range, Vp-p22
InterfaceDDR LVDS,Parallel CMOSDDR LVDS,Parallel CMOS
Operating Temperature Range, C-40 to 85-40 to 85
Package GroupVQFNVQFN
Package Size: mm2:W x L, PKG64VQFN: 81 mm2: 9 x 9(VQFN)64VQFN: 81 mm2: 9 x 9(VQFN)
Power Consumption(Typ), mW11401140
RatingCatalogCatalog
Reference ModeExt,IntExt,Int
Resolution, Bits1212
SFDR, dB8585
SINAD, dB70.570.5
SNR, dB70.670.6
Sample Rate(Max), MSPS210210

生态计划

ADS62P28IRGCRADS62P28IRGCT
RoHSCompliantCompliant

应用须知

  • QFN Layout Guidelines
    PDF, 1.3 Mb, 档案已发布: Jul 28, 2006
    Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015

模型线

系列: ADS62P28 (2)

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)