Datasheet Texas Instruments ADS5521 — 数据表

制造商Texas Instruments
系列ADS5521
Datasheet Texas Instruments ADS5521

12位,105MSPS模数转换器(ADC)

数据表

12-Bit, 105MSPS Analog-to-Digital Converter datasheet
PDF, 689 Kb, 修订版: D, 档案已发布: Oct 30, 2008
从文件中提取

价格

状态

ADS5521IPAPADS5521IPAPRADS5521IPAPRG4
Lifecycle StatusActive (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Obsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNoNoNo

打包

ADS5521IPAPADS5521IPAPRADS5521IPAPRG4
N123
Pin646464
Package TypePAPPAPPAP
Industry STD TermHTQFPHTQFPHTQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY160
CarrierJEDEC TRAY (10+1)
Device MarkingADS5521I
Width (mm)101010
Length (mm)101010
Thickness (mm)111
Pitch (mm).5.5.5
Max Height (mm)1.21.21.2
Mechanical Data下载下载下载

参数化

Parameters / ModelsADS5521IPAP
ADS5521IPAP
ADS5521IPAPR
ADS5521IPAPR
ADS5521IPAPRG4
ADS5521IPAPRG4
# Input Channels111
Analog Input BW, MHz750
Analog Input BW(MHz)750750
Approx. Price (US$)36.79 | 1ku36.79 | 1ku
ArchitecturePipelinePipelinePipeline
DNL(Max), +/-LSB0.25
DNL(Max)(+/-LSB)0.250.25
DNL(Typ), +/-LSB0.25
ENOB, Bits11.3
ENOB(Bits)11.311.3
INL(Max), +/-LSB0.5
INL(Max)(+/-LSB)0.50.5
INL(Typ), +/-LSB0.5
Input BufferNoNoNo
Input Range2.32.3V (p-p)2.3V (p-p)
InterfaceParallel CMOSParallel CMOS
Serial SPI Interface
Parallel CMOS
Serial SPI Interface
Operating Temperature Range, C-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Package GroupHTQFPHTQFPHTQFP
Package Size: mm2:W x L, PKG64HTQFP: 144 mm2: 12 x 12(HTQFP)
Package Size: mm2:W x L (PKG)64HTQFP: 144 mm2: 12 x 12(HTQFP)64HTQFP: 144 mm2: 12 x 12(HTQFP)
Power Consumption(Typ), mW736
Power Consumption(Typ)(mW)736736
RatingCatalogCatalogCatalog
Reference ModeIntIntInt
Resolution, Bits12
Resolution(Bits)1212
SFDR, dB86
SFDR(dB)8686
SINAD, dB70
SINAD(dB)7070
SNR, dB70.5
SNR(dB)70.570.5
Sample Rate(Max), MSPS105
Sample Rate(Max)(MSPS)105105

生态计划

ADS5521IPAPADS5521IPAPRADS5521IPAPRG4
RoHSCompliantNot CompliantNot Compliant
Pb FreeNoNo

应用须知

  • Clocking High-Speed Data Converters
    PDF, 310 Kb, 档案已发布: Jan 18, 2005
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • Interleaving Analog-to-Digital Converters
    PDF, 64 Kb, 档案已发布: Oct 2, 2000
    It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error.
  • What Designers Should Know About Data Converter Drift
    PDF, 95 Kb, 档案已发布: Oct 2, 2000
    Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.

模型线

制造商分类

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)