Datasheet Texas Instruments ADC32RF45 — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADC32RF45 |
双通道，14位，3GSPS RF采样模数转换器（ADC）
数据表
ADC32RF45 Dual-Channel, 14-Bit, 3.0-GSPS, Analog-to-Digital Converter datasheet
PDF, 7.3 Mb, 修订版: C, 档案已发布: Dec 6, 2016
从文件中提取
价格
状态
| ADC32RF45IRMP | ADC32RF45IRMPT | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No |
打包
| ADC32RF45IRMP | ADC32RF45IRMPT | |
|---|---|---|
| N | 1 | 2 |
| Pin | 72 | 72 |
| Package Type | RMP | RMP |
| Industry STD Term | VQFNP | VQFNP |
| JEDEC Code | S-PQFP-N | S-PQFP-N |
| Package QTY | 1 | 250 |
| Carrier | JEDEC TRAY (5+1) | SMALL T&R |
| Device Marking | AZ32RF45 | AZ32RF45 |
| Width (mm) | 10 | 10 |
| Length (mm) | 10 | 10 |
| Thickness (mm) | .9 | .9 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1 | 1 |
| Mechanical Data | 下载 | 下载 |
参数化
| Parameters / Models | ADC32RF45IRMP | ADC32RF45IRMPT |
|---|---|---|
| # Input Channels | 2 | 2 |
| Analog Input BW, MHz | 3200 | 3200 |
| Architecture | Pipeline | Pipeline |
| ENOB, Bits | 9.7 | 9.7 |
| Input Buffer | Yes | Yes |
| Input Range, Vp-p | 1.35 | 1.35 |
| Interface | JESD204B | JESD204B |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Package Group | VQFN | VQFN |
| Package Size: mm2:W x L, PKG | 72VQFN: 100 mm2: 10 x 10(VQFN) | 72VQFN: 100 mm2: 10 x 10(VQFN) |
| Power Consumption(Typ), mW | 6400 | 6400 |
| Rating | Catalog | Catalog |
| Reference Mode | Int | Int |
| Resolution, Bits | 14 | 14 |
| SFDR, dB | 67 | 67 |
| SINAD, dB | 60.2 | 60.2 |
| SNR, dB | 60.9 | 60.9 |
| Sample Rate(Max), MSPS | 3000 | 3000 |
生态计划
| ADC32RF45IRMP | ADC32RF45IRMPT | |
|---|---|---|
| RoHS | Compliant | Compliant |
应用须知
- How unmatched impedance at the clock input of an RF ADC affects SNR and jitterPDF, 2.3 Mb, 档案已发布: Jul 21, 2016
- Implementing JESD204B SYSREF and Achieving Deterministic Latency with ADC32RF45PDF, 105 Kb, 档案已发布: May 10, 2016
ADC32RF45 Implementing JESD204B SYSREF and achieving deterministic latency with ADC32RF45 ADC32RF45_SBAA221 HPA/HSP/HS_DC/App_Reports - S-Parameters for ADC32RF45: Modeling and ApplicationPDF, 1.8 Mb, 档案已发布: May 16, 2016
- Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B)ZIP, 211 Kb, 修订版: B, 档案已发布: Sep 5, 2017
- Clocking Optimization for RF Sampling Analog-to-Digital ConvertersPDF, 261 Kb, 档案已发布: May 17, 2016
- ADC32RF45: Amplifier to ADC Interface (Rev. A)PDF, 176 Kb, 修订版: A, 档案已发布: Sep 7, 2016
- RF Sampling ADC with 800MHz of IBW LTEPDF, 846 Kb, 档案已发布: Sep 8, 2016
模型线
系列: ADC32RF45 (2)
制造商分类
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)