Datasheet Texas Instruments ADC12D1600QML-SP — 数据表
| 制造商 | Texas Instruments |
| 系列 | ADC12D1600QML-SP |
12位，双1.6GSPS或单3.2GSPS，RF采样模数转换器（ADC）
数据表
ADC12D1600QML 12-Bit, 3.2/2.0 GSPS RF Sampling ADC datasheet
PDF, 904 Kb, 档案已发布: Dec 17, 2012
从文件中提取
价格
状态
| ADC12D1600CCMLS | ADC12D1600CCMPR | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No |
打包
| ADC12D1600CCMLS | ADC12D1600CCMPR | |
|---|---|---|
| N | 1 | 2 |
| Pin | 376 | 376 |
| Package Type | NAA | NAA |
| Industry STD Term | CCGA | CCGA |
| JEDEC Code | S-CBGA-N | S-CBGA-N |
| Package QTY | 1 | 1 |
| Carrier | TUBE | EIAJ TRAY (10+1) |
| Device Marking | ADC12D1600CC | MPR E.S. |
| Width (mm) | 27.94 | 27.94 |
| Length (mm) | 27.94 | 27.94 |
| Thickness (mm) | 2.79 | 2.79 |
| Pitch (mm) | 1.27 | 1.27 |
| Max Height (mm) | 3.5 | 3.5 |
| Mechanical Data | 下载 | 下载 |
参数化
| Parameters / Models | ADC12D1600CCMLS | ADC12D1600CCMPR |
|---|---|---|
| # Input Channels | 2,1 | 2,1 |
| Analog Input BW, MHz | 2400 | 2400 |
| Architecture | Folding Interpolating | Folding Interpolating |
| DNL(Max), +/-LSB | 0.5 | 0.5 |
| DNL(Typ), +/-LSB | 0.5 | 0.5 |
| ENOB, Bits | 8.9 | 8.9 |
| INL(Max), +/-LSB | 2.5 | 2.5 |
| INL(Typ), +/-LSB | 2.5 | 2.5 |
| Input Buffer | Yes | Yes |
| Input Range, Vp-p | 0.8 | 0.8 |
| Interface | Parallel LVDS | Parallel LVDS |
| Operating Temperature Range, C | -55 to 125,25 to 25 | -55 to 125,25 to 25 |
| Package Group | CCGA | CCGA |
| Package Size: mm2:W x L, PKG | 376CCGA: 781 mm2: 27.94 x 27.94(CCGA) | 376CCGA: 781 mm2: 27.94 x 27.94(CCGA) |
| Power Consumption(Typ), mW | 3880 | 3880 |
| Rating | Space | Space |
| Reference Mode | Int | Int |
| Resolution, Bits | 12 | 12 |
| SFDR, dB | 61.5 | 61.5 |
| SINAD, dB | 55.4 | 55.4 |
| SNR, dB | 56.6 | 56.6 |
| Sample Rate(Max), MSPS | 1600,3200 | 1600,3200 |
生态计划
| ADC12D1600CCMLS | ADC12D1600CCMPR | |
|---|---|---|
| RoHS | See ti.com | See ti.com |
应用须知
- Signal Chain Noise Figure AnalysisPDF, 615 Kb, 档案已发布: Oct 29, 2014
- Wide Bandwidth Receiver Implementation by Interleaving Two Giga-Sampling ADCsPDF, 621 Kb, 档案已发布: Dec 7, 2015
- Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAsPDF, 943 Kb, 档案已发布: Aug 6, 2014
- AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C)PDF, 60 Kb, 修订版: C, 档案已发布: May 1, 2013
In order to facilitate upgrading applications from a 10-bit Gig ADC to a 12-bit Gig ADC, the ADC10D1x00(ADC10D1500/ADC10D1000) is designed to be pin-compatible with the ADC12D1x00(ADC12D1800/1600/1000). This means that a single board layout may be designed with both resolutionADCs in mind for more cost efficient and time-to-market product development. - From Sample Instant to Data Output: Understanding Latency in the GSPS ADCPDF, 392 Kb, 档案已发布: Dec 18, 2012
For many applications which use ultra high-speed ADCs, latency can be a critical performance specification. For example, if the ADC is used in any kind of feedback loop, then the absolute latency is an important factor. For a MIMO system such as a phased array radar, the relative difference and variability in latency becomes important. This application note covers latency in the GSPS ADC products, - AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G)PDF, 169 Kb, 修订版: G, 档案已发布: Feb 3, 2017
模型线
系列: ADC12D1600QML-SP (2)
制造商分类
- Semiconductors> Space & High Reliability> Data Converter> Analog to Digital Converters