Datasheet Texas Instruments 74ACT11074 — 数据表

制造商Texas Instruments
系列74ACT11074
Datasheet Texas Instruments 74ACT11074

具有清零和预置功能的双路上升沿触发D型触发器

数据表

Dual D-Type Positive-Edge-Triggered Flip Flop With Clear And Preset datasheet
PDF, 877 Kb, 修订版: A, 档案已发布: Apr 1, 1996
从文件中提取

价格

状态

74ACT11074D74ACT11074DBLE74ACT11074DBR74ACT11074DG474ACT11074N74ACT11074NSR
Lifecycle StatusActive (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNo

打包

74ACT11074D74ACT11074DBLE74ACT11074DBR74ACT11074DG474ACT11074N74ACT11074NSR
N123456
Pin141414141414
Package TypeDDBDBDNNS
Industry STD TermSOICSSOPSSOPSOICPDIPSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDIP-TR-PDSO-G
Package QTY50200050252000
CarrierTUBELARGE T&RTUBETUBELARGE T&R
Device MarkingACT11074AT074ACT1107474ACT11074NACT11074
Width (mm)3.915.35.33.916.355.3
Length (mm)8.656.26.28.6519.310.3
Thickness (mm)1.581.951.951.583.91.95
Pitch (mm)1.27.65.651.272.541.27
Max Height (mm)1.75221.755.082
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参数化

Parameters / Models74ACT11074D
74ACT11074D
74ACT11074DBLE
74ACT11074DBLE
74ACT11074DBR
74ACT11074DBR
74ACT11074DG4
74ACT11074DG4
74ACT11074N
74ACT11074N
74ACT11074NSR
74ACT11074NSR
3-State OutputNoNoNoNoNoNo
Approx. Price (US$)0.94 | 1ku
Bits22222
Bits(#)2
F @ Nom Voltage(Max), Mhz9090909090
F @ Nom Voltage(Max)(Mhz)90
ICC @ Nom Voltage(Max), mA0.040.040.040.040.04
ICC @ Nom Voltage(Max)(mA)0.04
Input TypeTTL
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85
Output Drive (IOL/IOH)(Max), mA24/-2424/-2424/-2424/-2424/-24
Output Drive (IOL/IOH)(Max)(mA)24/-24
Output TypeCMOS
Package GroupSOICSSOPSSOPSOICPDIPSO
Package Size: mm2:W x L, PKG14SOIC: 52 mm2: 6 x 8.65(SOIC)14SSOP: 48 mm2: 7.8 x 6.2(SSOP)14SOIC: 52 mm2: 6 x 8.65(SOIC)See datasheet (PDIP)14SO: 80 mm2: 7.8 x 10.2(SO)
Package Size: mm2:W x L (PKG)See datasheet (PDIP)
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNo
Technology FamilyACTACTACTACTACTACT
VCC(Max), V5.55.55.55.55.5
VCC(Max)(V)5.5
VCC(Min), V4.54.54.54.54.5
VCC(Min)(V)4.5
Voltage(Nom), V55555
Voltage(Nom)(V)5
tpd @ Nom Voltage(Max), ns9.49.49.49.49.4
tpd @ Nom Voltage(Max)(ns)9.4

生态计划

74ACT11074D74ACT11074DBLE74ACT11074DBR74ACT11074DG474ACT11074N74ACT11074NSR
RoHSCompliantNot CompliantCompliantCompliantCompliantCompliant
Pb FreeYesNo

应用须知

  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, 修订版: A, 档案已发布: Jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Introduction to Logic
    PDF, 93 Kb, 档案已发布: Apr 30, 2015
  • Implications of Slow or Floating CMOS Inputs (Rev. D)
    PDF, 260 Kb, 修订版: D, 档案已发布: Jun 23, 2016
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, 修订版: C, 档案已发布: Dec 2, 2015
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, 档案已发布: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • TI IBIS File Creation Validation and Distribution Processes
    PDF, 380 Kb, 档案已发布: Aug 29, 2002
    The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
  • CMOS Power Consumption and CPD Calculation (Rev. B)
    PDF, 89 Kb, 修订版: B, 档案已发布: Jun 1, 1997
    Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
  • Power-Up Behavior of Clocked Devices (Rev. A)
    PDF, 34 Kb, 修订版: A, 档案已发布: Feb 6, 2015
  • Designing With Logic (Rev. C)
    PDF, 186 Kb, 修订版: C, 档案已发布: Jun 1, 1997
    Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, 档案已发布: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

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制造商分类

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop