SCAS521F -AUGUST 1995 -REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation
D Inputs Accept Voltages to 6 V
D Max tpd of 10 ns at 5 V SN54AC74 . J OR W PACKAGE
SN74AC74 . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW) 1CLR
1D
1CLK
1PRE
1Q
1Q
GND description/ordering information
The ’AC74 devices are dual positive-edgetriggered D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels
of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data …
