[ /Title
(CD74H
C109,
CD74H
CT109)
/Subject
(Dual JK FlipFlop
with Set
and
Reset CD54HC109, CD74HC109,
CD54HCT109, CD74HCT109
Data sheet acquired from Harris Semiconductor
SCHS140E Dual J-K Flip-Flop with Set and Reset
Positive-Edge Trigger March 1998 -Revised October 2003 Features Description Asynchronous Set and Reset The ’HC109 and ’HCT109 are dual J-K flip-flops with set and
reset. The flip-flop changes state with the positive transition
of Clock (1CP and 2CP). Schmitt Trigger Clock Inputs Typical fMAX = 54MHz at VCC = 5V, CL = 15pF,
TA = 25oC The flip-flop is set and reset by active-low S and R,
respectively. A low on both the set and reset inputs
simultaneously will force both Q and Q outputs high.
However, both set and reset going high simultaneously
results in an unpredictable output condition. Fanout (Over Temperature Range)
-Standard Outputs . 10 LSTTL Loads
-Bus Driver Outputs . 15 LSTTL Loads Ordering Information Wide Operating Temperature Range . -55oC to 125oC Balanced Propagation Delay and Transition Times PART NUMBER Significant Power Reduction Compared to LSTTL …
