Datasheet Texas Instruments ADS5240IPAP — 数据表

制造商Texas Instruments
系列ADS5240
零件号ADS5240IPAP
Datasheet Texas Instruments ADS5240IPAP

四通道,12位,40MSPS模数转换器(ADC)64-HTQFP -40至85

数据表

4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface datasheet
PDF, 1.2 Mb, 修订版: E, 档案已发布: Jan 6, 2009
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin64
Package TypePAP
Industry STD TermHTQFP
JEDEC CodeS-PQFP-G
Package QTY160
CarrierJEDEC TRAY (10+1)
Device MarkingADS5240IPAP
Width (mm)10
Length (mm)10
Thickness (mm)1
Pitch (mm).5
Max Height (mm)1.2
Mechanical Data下载

参数化

# Input Channels4
Analog Input BW300 MHz
ArchitecturePipeline
DNL(Max)0.9 +/-LSB
DNL(Typ)0.4 +/-LSB
ENOB11.3 Bits
INL(Max)2 +/-LSB
INL(Typ)0.75 +/-LSB
Input BufferNo
Input Range1 Vp-p
InterfaceParallel LVDS
Operating Temperature Range-40 to 85 C
Package GroupHTQFP
Package Size: mm2:W x L64HTQFP: 144 mm2: 12 x 12(HTQFP) PKG
Power Consumption(Typ)607 mW
RatingCatalog
Reference ModeExt,Int
Resolution12 Bits
SFDR85 dB
SINAD70 dB
SNR70.5 dB
Sample Rate(Max)40 MSPS

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • Interfacing High-Speed LVDS Outputs of the ADS527x/ADS524x
    PDF, 67 Kb, 档案已发布: Feb 23, 2005
    The ADS527x and ADS524x families of devices are high-performance octal/quad channel analog-to-digital converters, ideal for the highest system density. Serial low voltage differential signaling (LVDS) outputs reduce the number of I/O interfaces required, power and overall package size. These device families are rated to work from sampling rates of 20MSPS to 70MSPS, corresponding to data rates of 2
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015

模型线

制造商分类

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)