Datasheet Texas Instruments ADS821E/1K — 数据表

制造商Texas Instruments
系列ADS821
零件号ADS821E/1K
Datasheet Texas Instruments ADS821E/1K

具有Int基准和9.3位ENOB 28-SSOP的10位40 MSPS ADC SE / Diff输入-40至85

数据表

10-Bit, 40MHz Sampling Analog-To-Digital Converter datasheet
PDF, 388 Kb, 修订版: B, 档案已发布: Feb 14, 2005
从文件中提取

价格

状态

Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNo

打包

Pin28
Package TypeDB
Industry STD TermSSOP
JEDEC CodeR-PDSO-G
Width (mm)5.3
Length (mm)10.2
Thickness (mm)1.95
Pitch (mm).65
Max Height (mm)2
Mechanical Data下载

替代品

ReplacementADS825E/1K
Replacement CodeF

参数化

# Input Channels1
Analog Input BW(MHz)65
Approx. Price (US$)19.91 | 1ku
ArchitecturePipeline
DNL(Max)(+/-LSB)1
ENOB(Bits)9.3
INL(Max)(+/-LSB)2
Input BufferNo
Input Range2V (p-p)
InterfaceParallel CMOS
Operating Temperature Range(C)-40 to 85
Package GroupSOIC
Package Size: mm2:W x L (PKG)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)
Power Consumption(Typ)(mW)390
RatingCatalog
Reference ModeExt
Int
Resolution(Bits)10
SFDR(dB)62
SINAD(dB)58
SNR(dB)58
Sample Rate(Max)(MSPS)40

生态计划

RoHSNot Compliant
Pb FreeNo

设计套件和评估模块

  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200EVM: Low Cost Portable Power Supply
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Interleaving Analog-to-Digital Converters
    PDF, 64 Kb, 档案已发布: Oct 2, 2000
    It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration several possible sources of error.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • ADS82x ADC with non-uniform sampling clock
    PDF, 234 Kb, 档案已发布: Feb 28, 2005
  • What Designers Should Know About Data Converter Drift
    PDF, 95 Kb, 档案已发布: Oct 2, 2000
    Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its operating-temperature extremes, perhaps only to 9 or even 8 bits. But for lack of more precise knowledge, many play it safe (and expensive) and overspecify.
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.

模型线

系列: ADS821 (3)

制造商分类

  • Semiconductors > Data Converters > Analog to Digital Converter > High Speed ADC (>10MSPS)