[ /Title
(CD74
HC597
,
CD74
HCT59
7)
/Subject
(High
Speed
CMOS CD54HC597, CD74HC597,
CD74HCT597
Data sheet acquired from Harris Semiconductor
SCHS191C High-Speed CMOS Logic
8-Bit Shift Register with Input Storage January 1998 -Revised October 2003 Features Description Buffered Inputs The ’HC597 and CD74HCT597 are high-speed silicon gate
CMOS devices that are pin-compatible with the LSTTL 597
devices. Each device consists of an 8-flip-flop input register
and an 8-bit parallel-in/serial-in, serial-out shift register. Each
register is controlled by its own clock. A “low” on the parallel
load input (PL) shifts parallel stored data asynchronously into
the shift register. A “low” master input (MR) clears the shift
register. Serial input data can also be synchronously shifted
through the shift register when PL is high. Asynchronous Parallel Load Fanout (Over Temperature Range) …
