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Documents ADC34J22, ADC34J23, ADC34J24, ADC34J25
SBAS669A – MAY 2014 – REVISED JANUARY 2015 ADC34J2x Quad-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter
with JESD204B Interface
1 Features 3 Description The ADC34J2x are a high-linearity, ultra-low power,
dual-channel, 12-bit, 50-MSPS to 160-MSPS, analogto-digital converter (ADC) family. The devices are
designed specifically to support demanding, high
input frequency signals with large dynamic range
requirements. A clock input divider allows more
flexibility for system clock architecture design while
the SYSREF input enables complete system
synchronization. The devices support JESD204B
interfaces in order to reduce the number of interface
lines, thus allowing for high system integration
density. The JESD204B interface is a serial interface,
where the data of each ADC are serialized and output
over only one differential pair. An internal phaselocked loop (PLL) multiplies the incoming ADC
sampling clock by 20 to derive the bit clock that is
used to serialize the 12-bit data from each channel. …
