Datasheet Texas Instruments THS1041IDW — 数据表

制造商Texas Instruments
系列THS1041
零件号THS1041IDW
Datasheet Texas Instruments THS1041IDW

具有PGA和内部精密钳位的10位40MSPS低功耗ADC 28-SOIC -40至85

数据表

10-Bit, 40-MSPS Analog-to-Digital Converter With PGA and Clamp datasheet
PDF, 951 Kb, 修订版: C, 档案已发布: Oct 28, 2004
从文件中提取

价格

状态

Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNo

打包

Pin28
Package TypeDW
Industry STD TermSOIC
JEDEC CodeR-PDSO-G
Device MarkingTJ1041
Width (mm)7.5
Length (mm)17.9
Thickness (mm)2.35
Pitch (mm)1.27
Max Height (mm)2.65
Mechanical Data下载

替代品

ReplacementADC10040CIMTX/NOPB
Replacement CodeP

参数化

# Input Channels1
Analog Input BW(MHz)900
Approx. Price (US$)7.46 | 1ku
ArchitecturePipeline
DNL(Max)(+/-LSB)1
ENOB(Bits)9.5
INL(Max)(+/-LSB)1.5
Input BufferNo
Input Range2V (p-p)
InterfaceParallel CMOS
Operating Temperature Range(C)0 to 70
Package GroupTSSOP
Package Size: mm2:W x L (PKG)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Power Consumption(Typ)(mW)103
RatingCatalog
Reference ModeExt
Int
Resolution(Bits)10
SFDR(dB)70
SINAD(dB)60
SNR(dB)57
Sample Rate(Max)(MSPS)40

生态计划

RoHSNot Compliant
Pb FreeNo

设计套件和评估模块

  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200EVM: Low Cost Portable Power Supply
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • High-Speed ADC THS1041and FPGA Interface Considerations
    PDF, 130 Kb, 档案已发布: Mar 15, 2007
    The Texas Instruments THS1041 is a 10-bit, 40-MSPS, high-speed analog-to-digital converter (ADC). For many years because of its low power dissipation and extended life, it has been used in various applications such as programmable gain amplifier and built-in clamp. With recent FPGA development, some application systems have been upgraded with a direct interface of the THS1041 to an FPGA, for examp
  • Clamp function of high-speed ADC THS1041
    PDF, 235 Kb, 档案已发布: Oct 10, 2006
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, 修订版: A, 档案已发布: Jan 17, 2005
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

模型线

制造商分类

  • Semiconductors > Data Converters > Analog to Digital Converter > High Speed ADC (>10MSPS)