Datasheet Texas Instruments SN74ALVCH162721DGGR — 数据表

制造商Texas Instruments
系列SN74ALVCH162721
零件号SN74ALVCH162721DGGR
Datasheet Texas Instruments SN74ALVCH162721DGGR

具有三态输出的3.3V 20位触发器56-TSSOP -40至85

数据表

SN74ALVCH162721 datasheet
PDF, 339 Kb, 修订版: G, 档案已发布: Sep 17, 2004
从文件中提取

价格

状态

Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)
Manufacture's Sample AvailabilityNo

打包

Pin56
Package TypeDGG
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Width (mm)6.1
Length (mm)14
Thickness (mm)1.15
Pitch (mm).5
Max Height (mm)1.2
Mechanical Data下载

替代品

ReplacementSN74ALVCH162721GR
Replacement CodeS

参数化

3-State OutputYes
Approx. Price (US$)1.65 | 1ku
Bits(#)20
F @ Nom Voltage(Max)(Mhz)150
ICC @ Nom Voltage(Max)(mA)0.04
Input TypeLVTTL
CMOS
Operating Temperature Range(C)-40 to 85
Output Drive (IOL/IOH)(Max)(mA)12/-12
Output TypeLVTTL
CMOS
Package GroupTSSOP
Package Size: mm2:W x L (PKG)56TSSOP: 113 mm2: 8.1 x 14(TSSOP)
RatingCatalog
Schmitt TriggerNo
Technology FamilyALVC
VCC(Max)(V)3.6
VCC(Min)(V)1.65
Voltage(Nom)(V)1.8
2.5
2.7
3.3
tpd @ Nom Voltage(Max)(ns)6.7
6.2
5.3

生态计划

RoHSNot Compliant
Pb FreeNo

应用须知

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, 档案已发布: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, 修订版: A, 档案已发布: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • Bus-Hold Circuit
    PDF, 418 Kb, 档案已发布: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, 修订版: A, 档案已发布: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families

模型线

制造商分类

  • Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop