Datasheet Texas Instruments CD54HCT4046AF3A — 数据表

制造商Texas Instruments
系列CD54HCT4046A
零件号CD54HCT4046AF3A
Datasheet Texas Instruments CD54HCT4046AF3A

带有VCO 16-CDIP -55至125的高速CMOS逻辑锁相环

数据表

CD54HC4046A, CD74HC4046A, CD54HCT4046A, CD74HCT4046A datasheet
PDF, 833 Kb, 修订版: J, 档案已发布: Nov 21, 2003
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin16
Package TypeJ
Industry STD TermCDIP
JEDEC CodeR-GDIP-T
Package QTY1
CarrierTUBE
Width (mm)6.92
Length (mm)19.56
Thickness (mm)4.57
Pitch (mm)2.54
Max Height (mm)5.08
Mechanical Data下载

参数化

Bits1
F @ Nom Voltage(Max)25 Mhz
ICC @ Nom Voltage(Max)0.08 mA
Input TypeTTL
Operating Temperature Range-55 to 125 C
Output Drive (IOL/IOH)(Max)4/-4 mA
Output TypeCMOS
Package GroupCDIP
Package Size: mm2:W x LSee datasheet (CDIP) PKG
RatingMilitary
Schmitt TriggerNo
Technology FamilyHCT
VCC(Max)5.5 V
VCC(Min)4.5 V
Voltage(Nom)4.5 V
tpd @ Nom Voltage(Max)85 ns

生态计划

RoHSSee ti.com

应用须知

  • Implementation of FSK Modulation and Demodulation using CD74HC4046A
    PDF, 1.3 Mb, 档案已发布: Nov 25, 2013
  • CMOS Phase-Locked-Loop Applications (Rev. B)
    PDF, 687 Kb, 修订版: B, 档案已发布: Sep 19, 2002
    Applications of the HC/HCT4046A phase-locked loop (PLL) and HC/HCT7046A PLL with lock detection are provided including design examples with calculated and measured results. Features of these devices relative to phase comparators lock indicators voltage-controlled oscillators (VCOs) and filter design are presented.
  • SN54/74HCT CMOS Logic Family Applications and Restrictions
    PDF, 102 Kb, 档案已发布: May 1, 1996
    The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal
  • TI IBIS File Creation Validation and Distribution Processes
    PDF, 380 Kb, 档案已发布: Aug 29, 2002
    The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
  • Implications of Slow or Floating CMOS Inputs (Rev. D)
    PDF, 260 Kb, 修订版: D, 档案已发布: Jun 23, 2016
  • Designing With Logic (Rev. C)
    PDF, 186 Kb, 修订版: C, 档案已发布: Jun 1, 1997
    Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
  • CMOS Power Consumption and CPD Calculation (Rev. B)
    PDF, 89 Kb, 修订版: B, 档案已发布: Jun 1, 1997
    Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, 修订版: C, 档案已发布: Dec 2, 2015
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, 档案已发布: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, 档案已发布: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
  • Introduction to Logic
    PDF, 93 Kb, 档案已发布: Apr 30, 2015

模型线

系列: CD54HCT4046A (2)

制造商分类

  • Semiconductors > Space & High Reliability > Logic Products > Specialty Logic Products > Phase-Locked-Loop (PLL)Products/Oscillators