[ /Title
(CD74
HC192
,
CD74
HC193
,
CD74
HCT19
3)
/Subject
(High
Speed
CMOS
Logic
Preset-CD54/74HC192,
CD54/74HC193, CD54/74HCT193
Data sheet acquired from Harris Semiconductor
SCHS163F September 1997 -Revised October 2003 High-Speed CMOS Logic
Presettable Synchronous 4-Bit Up/Down Counters Features Presetting the counter to the number on the preset data inputs
(P0-P3) is accomplished by a LOW asynchronous parallel
load input (PL). The counter is incremented on the low-to-high
transition of the Clock-Up input (and a high level on the ClockDown input) and decremented on the low to high transition of …
