[ /Title
(CD74
HC393
,
CD74
HCT39
3)
/Subject
(High
Speed
CMOS CD54HC393, CD74HC393,
CD54HCT393, CD74HCT393
Data sheet acquired from Harris Semiconductor
SCHS186E High-Speed CMOS Logic
Dual 4-Stage Binary Counter September 1997 -Revised August 2003 Features Description Fully Static Operation The ’HC393 and ’HCT393 are 4-stage ripple-carry binary
counters. All counter stages are master-slave flip-flops. The
state of the stage advances one count on the negative
transition of each clock pulse; a high voltage level on the MR
line resets all counters to their zero state. All inputs and
outputs are buffered. Buffered Inputs Common Reset Negative-Edge Clocking Fanout (Over Temperature Range) Ordering Information -Standard Outputs . 10 LSTTL Loads
-Bus Driver Outputs . 15 LSTTL Loads PART NUMBER Wide Operating Temperature Range . -55oC to 125oC TEMP. RANGE
(oC) PACKAGE Balanced Propagation Delay and Transition Times CD54HC393F3A -55 to 125 14 Ld CERDIP Significant Power Reduction Compared to LSTTL
Logic ICs CD54HCT393F3A -55 to 125 14 Ld CERDIP CD74HC393E -55 to 125 14 Ld PDIP CD74HC393M -55 to 125 14 Ld SOIC CD74HC393MT -55 to 125 14 Ld SOIC CD74HC393M96 -55 to 125 14 Ld SOIC CD74HCT393E -55 to 125 14 Ld PDIP CD74HCT393M -55 to 125 14 Ld SOIC CD74HCT393MT -55 to 125 14 Ld SOIC CD74HCT393M96 -55 to 125 14 Ld SOIC HC Types …
