Datasheet Texas Instruments ADS5400MHFSV — 数据表

制造商Texas Instruments
系列ADS5400-SP
零件号ADS5400MHFSV
Datasheet Texas Instruments ADS5400MHFSV

12位1.0GSPS模数转换器(ADC)100-CFP -55至125

数据表

12-Bit, 1-GSPS Analog-to-Digital Converter. datasheet
PDF, 1.1 Mb, 修订版: D, 档案已发布: Jan 2, 2014
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin100100100100
Package TypeHFSHFSHFSHFS
Industry STD TermCFP (TBAR)CFP (TBAR)CFP (TBAR)CFP (TBAR)
JEDEC CodeS-CQFP-FS-CQFP-FS-CQFP-FS-CQFP-F
Package QTY1111
Device MarkingADS5400MHFSV5962-0924001VXCADS5400MHFS-V
Width (mm)19.0519.0519.0519.05
Length (mm)19.0519.0519.0519.05
Thickness (mm)2.822.822.822.82
Pitch (mm).5.5.5.5
Max Height (mm)3.153.153.153.15
Mechanical Data下载下载下载下载

参数化

# Input Channels1
Analog Voltage AVDD(Max)3.465 V
Analog Voltage AVDD(Min)3.135 V
ArchitecturePipeline
Digital Supply(Max)3.465 V
Digital Supply(Min)3.135 V
ENOB9.2 Bits
INL(Max)4.5 +/-LSB
INL(Typ)1.5 +/-LSB
InterfaceParallel LVDS
Operating Temperature Range-55 to 125,25 Only C
Package GroupCFP
Package Size: mm2:W x LSee datasheet (CFP) PKG
Power Consumption(Typ)2200 mW
RatingSpace
Reference ModeExt,Int
Resolution12 Bits
SFDR72 dB
SNR58.5 dB
Sample Rate (max)1GSPS SPS

生态计划

RoHSSee ti.com

设计套件和评估模块

  • Evaluation Modules & Boards: ADS5400EVM
    ADS5400 12-bit, 1.0-GSPS Analog-to-Digital Converter Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: ADS5400EVM-CVAL
    ADS5400-SP Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, 档案已发布: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015

模型线

系列: ADS5400-SP (3)

制造商分类

  • Semiconductors > Space & High Reliability > Data Converter > Analog to Digital Converters