Datasheet Texas Instruments DAC5681IRGCT — 数据表

制造商Texas Instruments
系列DAC5681
零件号DAC5681IRGCT
Datasheet Texas Instruments DAC5681IRGCT

16位1.0GSPS数模转换器(DAC)64-VQFN -40至85

数据表

16-bit 1.0 GSPS Digital-To-Analog Converter (DAC) . datasheet
PDF, 2.1 Mb, 修订版: C, 档案已发布: Aug 6, 2012
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityYes

打包

Pin64
Package TypeRGC
Industry STD TermVQFN
JEDEC CodeS-PQFP-N
Package QTY250
CarrierSMALL T&R
Device MarkingDAC5681I
Width (mm)9
Length (mm)9
Thickness (mm).88
Pitch (mm).5
Max Height (mm)1
Mechanical Data下载

参数化

ArchitectureCurrent Sink
DAC Channels1
InterfaceParallel LVDS
Interpolation1x
Operating Temperature Range-40 to 85 C
Package GroupVQFN
Package Size: mm2:W x L64VQFN: 81 mm2: 9 x 9(VQFN) PKG
Power Consumption(Typ)650 mW
RatingCatalog
Resolution16 Bits
SFDR81 dB
Sample / Update Rate1000 MSPS

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: FMC-DAC-ADAPTER
    High Speed DAC to FMC (Xilinx) Header Adapter Card
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: DAC5681EVM
    DAC5681 16-Bit, 1.0-GSPS Digital-to-Analog Converter Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: DAC5681ZEVM
    DAC5681Z 16-Bit, 1.0-GSPS, 1x-4x Interpolating Digital-to-Analog Converter Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: DAC5682ZEVM
    DAC5682Z Dual-Channel, 16-Bit, 1.0-GSPS Digital-to-Analog Converter Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: TSW3100EVM
    TSW3100 Pattern Generator Module
    Lifecycle Status: Obsolete (Manufacturer has discontinued the production of the device)
  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs
    PDF, 319 Kb, 档案已发布: Jul 14, 2009
  • Passive Terminations for Current Output DACs
    PDF, 244 Kb, 档案已发布: Nov 10, 2008
    The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
  • Q3 2009 Issue Analog Applications Journal
    PDF, 2.1 Mb, 档案已发布: Jul 14, 2009
  • High Speed Digital-to-Analog Converters Basics (Rev. A)
    PDF, 829 Kb, 修订版: A, 档案已发布: Oct 23, 2012
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

模型线

系列: DAC5681 (2)

制造商分类

  • Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)