Datasheet Texas Instruments SN74ALVC125PW — 数据表

制造商Texas Instruments
系列SN74ALVC125
零件号SN74ALVC125PW
Datasheet Texas Instruments SN74ALVC125PW

具有三态输出的四路总线缓冲门14-TSSOP -40至85

数据表

SN74ALVC125 datasheet
PDF, 615 Kb, 修订版: H, 档案已发布: Sep 17, 2004
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin14
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Package QTY90
CarrierTUBE
Device MarkingVA125
Width (mm)4.4
Length (mm)5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical Data下载

参数化

Bits4
F @ Nom Voltage(Max)100 Mhz
ICC @ Nom Voltage(Max)0.01 mA
Operating Temperature Range-40 to 85 C
Output Drive (IOL/IOH)(Max)-24/24 mA
Package GroupTSSOP
Package Size: mm2:W x L14TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG
RatingCatalog
Schmitt TriggerNo
Technology FamilyALVC
VCC(Max)3.6 V
VCC(Min)1.65 V
Voltage(Nom)1.8,2.5,2.7,3.3 V
tpd @ Nom Voltage(Max)5.3,3.2,3.1,2.8 ns

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: TMDXEVM388
    DM388 DaVinci Digital Media Processor Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • TI SN74ALVC16835 Component Specification Analysis for PC100
    PDF, 43 Kb, 档案已发布: Aug 3, 1998
    The PC100 standard establishes design parameters for the PC SDRAM DIMM that is designed to operate at 100 MHz. The 168-pin, 8-byte, registered SDRAM DIMM is a JEDEC-defined device (JC-42.5-96-146A). Some of the defined signal paths include data signals, address signals, and control signals. This application report discusses the SN74ALVC16835 18-bit universal bus driver that is available from T
  • Logic Solutions for PC-100 SDRAM Registered DIMMs (Rev. A)
    PDF, 96 Kb, 修订版: A, 档案已发布: May 13, 1998
    Design of high-performance personal computer (PC) systems that are capable of meeting the needs imposed by modern operating systems and software includes the use of large banks of SDRAMs on DIMMs (see Figure 1).To meet the demands of stable functionality over the broad spectrum of operating environments, meet system timing needs, and to support data integrity, the loads presented by the large
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, 修订版: B, 档案已发布: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
    PDF, 154 Kb, 修订版: A, 档案已发布: Sep 8, 1999
    In the last few years the trend toward reducing supply voltage (VCC) has continued as reflected in an additional specification of 2.5-V VCC for the AVC ALVT ALVC LVC LV and the CBTLV families.In this application report the different logic levels at VCC of 5 V 3.3 V 2.5 V and 1.8 V are compared. Within the report the possibilities for migration from 5-V logic and 3.3-V logic families
  • Understanding Advanced Bus-Interface Products Design Guide
    PDF, 253 Kb, 档案已发布: May 1, 1996

模型线

制造商分类

  • Semiconductors > Logic > Buffer/Driver/Transceiver > Non-Inverting Buffer/Driver