Datasheet Texas Instruments ADC31JB68RTA25 — 数据表

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Software ADC31JB68
SLASE60A – SEPTEMBER 2015 – REVISED SEPTEMBER 2015 ADC31JB68 Single Channel 16-bit 500 Msps Analog to Digital Converter
1 Features 2 Applications 1 Single Channel
16-Bit Resolution
Maximum Clock Rate: 500 Msps
Small 40-Pin QFN Package (6 x 6 mm)
Input Buffer Input Bandwidth (3 dB): 1300 MHz
Aperture Jitter: 80 fs
On Chip Clock Divider: /1, /2, /4
On Chip Dither
Consistent Dynamic Performance Using
Foreground and Background Calibration
Input Amplitude and Phase Adjustment
Input Full Scale: 1.7 Vpp
Power Supplies: 1.2/1.8/3 V
JESD204B Interface
– Subclass 1 Compliant
– 2 Lanes at 5 Gbps …