Datasheet Texas Instruments ADS5482IRGCR — 数据表

制造商Texas Instruments
系列ADS5482
零件号ADS5482IRGCR
Datasheet Texas Instruments ADS5482IRGCR

16位105MSPS模数转换器(ADC)64-VQFN -40至85

数据表

16-Bit, 80/105/135 MSPS High-Speed ADCs datasheet
PDF, 3.2 Mb, 修订版: C, 档案已发布: Oct 6, 2009
从文件中提取

价格

状态

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

打包

Pin64
Package TypeRGC
Industry STD TermVQFN
JEDEC CodeS-PQFP-N
Package QTY2000
CarrierLARGE T&R
Device MarkingAZ5482
Width (mm)9
Length (mm)9
Thickness (mm).88
Pitch (mm).5
Max Height (mm)1
Mechanical Data下载

参数化

# Input Channels1
Analog Input BW125 MHz
ArchitecturePipeline
DNL(Max)1 +/-LSB
DNL(Typ)0.5 +/-LSB
ENOB12.88 Bits
INL(Max)10 +/-LSB
INL(Typ)3 +/-LSB
Input BufferYes
Input Range3 Vp-p
InterfaceParallel LVDS
Operating Temperature Range-40 to 85 C
Package GroupVQFN
Package Size: mm2:W x L64VQFN: 81 mm2: 9 x 9(VQFN) PKG
Power Consumption(Typ)2100 mW
RatingCatalog
Reference ModeExt,Int
Resolution16 Bits
SFDR98 dB
SINAD79.3 dB
SNR80.5 dB
Sample Rate(Max)105 MSPS

生态计划

RoHSCompliant

设计套件和评估模块

  • Evaluation Modules & Boards: THS770006EVM
    THS770006 Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: TSW2200EVM
    TSW2200 Low-Cost Portable Power Supply Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: ADS5482EVM
    ADS5482 16-Bit, 105-MSPS Analog-to-Digital Converter Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: ADS5483EVM
    ADS5483 16-Bit, 135-MSPS Analog-to-Digital Converter Evaluation Module
    Lifecycle Status: Active (Recommended for new designs)

应用须知

  • Input Impedance Measurement Using ADC FFT Data
    PDF, 275 Kb, 档案已发布: Jan 11, 2011
    Texas Instruments has introduced a family of high-speed analog-to-digital converters (ADCs) suited tomeet the demand for high-speed and high-IF sampling systems. To achieve the highest overall system performance, an analog front-end circuit with an antialiasing filter must drive the ADC with the highestpossible dynamic range and lowest distortions. One important parameter of the front-end circ
  • High-Speed Analog-to-Digital Converter Basics
    PDF, 1.1 Mb, 档案已发布: Jan 11, 2012
    The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil
  • QFN Layout Guidelines
    PDF, 1.3 Mb, 档案已发布: Jul 28, 2006
    Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, 修订版: A, 档案已发布: May 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, 修订版: A, 档案已发布: Jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, 档案已发布: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, 修订版: A, 档案已发布: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, 档案已发布: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, 档案已发布: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, 修订版: A, 档案已发布: Apr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, 修订版: B, 档案已发布: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, 修订版: A, 档案已发布: May 18, 2015

模型线

系列: ADS5482 (2)

制造商分类

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)