Datasheet Texas Instruments PADC34J25IRGZT — 数据表

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SBAS669 ­ MAY 2014 ADC34J2x Quad-Channel, 12-Bit, 50-MSPS to 160-MSPS, Analog-to-Digital Converter with JESD204B Interface
1 Features 1 3 Description
The ADC34J2x are a high-linearity, ultra-low power, dual-channel, 12-bit, 50-MSPS to 160-MSPS, analogto-digital converter (ADC) family. The devices are designed specifically to support demanding, high input frequency signals with large dynamic range requirements. A clock input divider allows more flexibility for system clock architecture design while the SYSREF input enables complete system synchronization. The devices support serial lowvoltage differential signaling (LVDS) and JESD204B interfaces in order to reduce the number of interface lines, thus allowing for high system integration density. The JESD204B interface is a serial interface, where the data of each ADC are serialized and output over only one differential pair. An internal phaselocked loop (PLL) multiplies the incoming ADC sampling clock by 20 to derive the bit clock that is used to serialize the 12-bit data from each channel. The devices support subclass 1 with interface speeds up to 3.2 Gbps. Device Information(1)
PART NUMBER ADC34J22 ADC34J23 ADC34J24 ADC34J25 (1) For all available packages, see the orderable addendum at the end of the datasheet. VQFN (48) 7.00 mm Ч 7.00 mm PACKAGE BODY SIZE (NOM) 2 Applications Multi-Carrier, Multi-Mode Cellular Base Stations Radar and Smart Antenna Arrays Munitions Guidance Motor Control Feedback Network and Vector Analyzers Communications Test Equipment Nondestructive Testing Microwave Receivers Software Defined Radios (SDRs) Quadrature and Diversity Radio Receivers FFT with Dither On (fS = 160 MSPS, fIN = 10 MHz, SNR = 70.1 dBFS, SFDR = 95 dBc)
0 -20
Attenuation (dB) -40 -60 -80 -100 -120 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 Frequency (MHz) D001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of development. Subject to change or discontinuance without notice. PRODUCT PREVIEW Quad Channel 12-Bit Resolution Single 1.8-V Supply Flexible Input Clock Buffer with Divide-by-1, -2, -4 SNR = 70.3 dBFS, SFDR = 88 dBc at fIN = 70 MHz Ultra-Low Power Consumption: ­ 203 mW/Ch at 160 MSPS Channel Isolation: 105 dB Internal Dither JESD204B Serial Interface: ­ Subclass 0, 1, 2 Compliant u …