Datasheet PI6CB332000 (Diodes) - 9
| 制造商 | Diodes |
| 描述 | 20-Output PCIe G4 Clock Buffer With On-Chip Termination |
| 页数 / 页 | 21 / 9 — PI6CB332000. LVCMOS AC Electrical Characteristics. Symbol. Parameters. … |
| 文件格式/大小 | PDF / 1.5 Mb |
| 文件语言 | 英语 |
PI6CB332000. LVCMOS AC Electrical Characteristics. Symbol. Parameters. Conditions. Min. Typ. Max. Units. HCSL Input Characteristics(1)
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A product Line of Diodes Incorporated
PI6CB332000 LVCMOS AC Electrical Characteristics
Temperature = TA. Supply voltages per normal operation conditions. See test circuits for the load conditions.
Symbol Parameters Conditions Min. Typ. Max. Units
Q start after OE# assertion tOELAT Output Enable Latency 1 6 10 clocks Q stop after OE# deassertion tPDLAT PD# Deassertion Differential outputs enable after PD# deassertion — 200 300 µs
HCSL Input Characteristics(1)
Temperature = TA. Supply voltages per normal operation conditions. See test circuits for the load conditions.
Symbol Parameters Conditions Min. Typ. Max. Units
fIN Input Frequency — 1 100 200 MHz VIHDIF Diff. Input High Voltage (3) IN+, IN-, single-ended measurement 330 — 1150 mV VILDIF Diff. Input Low Voltage (3) IN+, IN-, single-ended measurement -300 0 300 mV VSWING Diff. Input Swing Voltage Peak-to-peak value (VIHDIF - VILDIF) 200 — — mV VCOM Common Mode Voltage — 0 — 900 mV tRF Diff. Input Slew Rate (2) — 0.7 — — V/ns IIN Diff. Input Leakage Current VIN = VDD, VIN = GND -5 — 5 µA tDC Diff. Input Duty Cycle Measured differentially 45 — 55 % tjc-c Diff. Input Cycle-to-Cycle Jitter Measured differentially — — 125 ps
Note:
1. Guaranteed by design and characterization—not 100% tested in production. 2. Slew rate measured through ±75mV window centered around differential zero. 3. The device can be driven by a single-ended clock by driving the true clock and biasing the complement clock input to the Vbias, where Vbias is (VIH-VIL)/2. PI6CB332000 www.diodes.com July 2019 Document Number DS41283 Rev 4-2 9 Diodes Incorporated
PI6CB332000 LVCMOS AC Electrical Characteristics
Temperature = TA. Supply voltages per normal operation conditions. See test circuits for the load conditions.
Symbol Parameters Conditions Min. Typ. Max. Units
Q start after OE# assertion tOELAT Output Enable Latency 1 6 10 clocks Q stop after OE# deassertion tPDLAT PD# Deassertion Differential outputs enable after PD# deassertion — 200 300 µs
HCSL Input Characteristics(1)
Temperature = TA. Supply voltages per normal operation conditions. See test circuits for the load conditions.
Symbol Parameters Conditions Min. Typ. Max. Units
fIN Input Frequency — 1 100 200 MHz VIHDIF Diff. Input High Voltage (3) IN+, IN-, single-ended measurement 330 — 1150 mV VILDIF Diff. Input Low Voltage (3) IN+, IN-, single-ended measurement -300 0 300 mV VSWING Diff. Input Swing Voltage Peak-to-peak value (VIHDIF - VILDIF) 200 — — mV VCOM Common Mode Voltage — 0 — 900 mV tRF Diff. Input Slew Rate (2) — 0.7 — — V/ns IIN Diff. Input Leakage Current VIN = VDD, VIN = GND -5 — 5 µA tDC Diff. Input Duty Cycle Measured differentially 45 — 55 % tjc-c Diff. Input Cycle-to-Cycle Jitter Measured differentially — — 125 ps
Note:
1. Guaranteed by design and characterization—not 100% tested in production. 2. Slew rate measured through ±75mV window centered around differential zero. 3. The device can be driven by a single-ended clock by driving the true clock and biasing the complement clock input to the Vbias, where Vbias is (VIH-VIL)/2. PI6CB332000 www.diodes.com July 2019 Document Number DS41283 Rev 4-2 9 Diodes Incorporated